Intel Xeon

Error reading llc_misses event in Xeon D-1540

Hello everyone, 

I am working in a tool that permits to access the different hardware events through performance counters (PMC). This tools works great I have tested in several Intel processors, SandyBridge, Haswell and Haswel-EP. Now I am working with a Broadwell processor that has some new cache monitoring features I need to work with. 

Trying my tool in this processor I found that the events, described in 64-ia-32-architectures-software-developer-manual-325462.pdf Table 19.1, LLC Reference (2EH, Umask 4FH) and LLC Misses (2EH, Umask 41H) report the same number. 

Xeon E5 MSR_PP1_ENERGY_STATUS read/write Error

http://web.eece.maine.edu/~vweaver/projects/rapl/rapl-read.c

 

I am using the above utility to determine the power consumption of Xeon E5 chip. When I execute the above code on my machine the output is

 

Found Haswell CPU
Checking core #0
Power units = 0.125W
Energy units = 0.00006104J
Time units = 0.00097656s

User programmable DMA controller in the system with Xeon E3-1275v3 and C226 PCH?

We are using Xeon E3-1275v3 and  C226 PCH on our board. I am aware that this system does not support I/OAT or NetDMA.

 

Is there any user programmable DMA controller?

 

We want to perform DMA transfers from the main memory (source) to PCIe devices (destination).

Note: PCIe devices do not have DMA controller. PCIe device (destination) can be either PCIe BAR in endpoint or multicast BAR residing inside PCIe switch.

ECC Error Injection on Xeon C5518

I am working on Error Detection module and was attempting to test using the error injection implementation mentioned in Intel® Xeon® Processor C5500/C3500 Series Datasheet, Volume 2  in section 4.12.40. It asks to program the MC_CHANNEL_X_ADDR_MATCH, MC_CHANNEL_X_ECC_ERROR_MASK and MC_CHANNEL_X_ECC_ERROR_MASK registers but attempting to write to this has no effect. Realized there is a lock for this space which is indicated by status in MEMLOCK_STATUS register (device 0: function 0: offset 88h), which in my case is reporting 0x40401 as the set value.

Memory copy using Intel Quickdata technology

I am doing the experimentation on improving the memory-to-memory copy performance (NIC to memory also, but secondary). I have seen that Intel I/OAT provides the Quickdata technology feature to offload the copies using DMA engine.

1. I haven't seen many i/oat related discussions in past few years, is it replaced with other more improved technology in new chipsets?

2. I need the Quickdata technology feature, how can I detect that my processor has Quickdata technology? In lspci, it is not showing anything related to Intel Quickdata Technology.

double parameter not copying correctly

We are attempting to use the rapidjson project (https://code.google.com/p/rapidjson/) to parse through a json file, but we get a segfault when running it natively on the Xeon Phi Linux enviroment.  It runs fine on the Xeon chip, however.  The segfault occurs in the following lines of code in the rapidjson project:

reader.h

d *= internal::Pow10(exp + expFrac);
handler.Double(minus ? -d : d);

document.h

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