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Développeurs, tirez parti de la technologie de virtualisation Intel® VT. Engagez la conversation avec les participants à nos blogs et au forum et dites-nous ce qui est important pour vous. Faites-nous savoir ce qui vous semble réussi et quelles opportunités nous pourrions présenter pour que ce site et les outils qui s’y trouvent soient plus pertinents pour ce que vous entreprenez de faire.

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Finding out if "Unrestricted Guest" supported at runtime
By johndoe314152
Hi there, is there an option to find out at runtime (e.g. with means of CPUID or something else) if the "Unrestricted Guest" feature is supported on the CPU? In the developer manual I can only find which flags control the UG feature (i.e. "25.8. Unrestricted Guests" ff), but I don't see anywhere how to determine if the feature is actually supported. Historically, at which processor family was "Unrestricted Guest" introduced? Is there a easy way to tell which processors contian the feature from the timeline? Best regards,Joe
Is it possible to use Intel NPT to do cross ISA memory translation?
By azru05121
O.K., I know Intel virtualization techniques are used to help better performance for same ISA, i.e., x86, virtualization. But I am curious if we can use NPT to help us to do cross ISA memory translation. For example, I can run a ARM guest on x86 host by using QEMU, but the memory translation inside QEMU is pure software. Is it possible to leverage underlying hardware to speedup the translation? Any comments are welcome. Thanks!
How to manually do VM exit in the guest?
By 1987102
I need to define a new exit reason of my own and want to set the exit reason in VMCS before switching to the host KVM module,then do something in KVM hypervisor for this reason.But I notice the vmcs_writel() is static,how can I do it?
Performance Counter Uncore issues
By heinerj1
Trying to implement performance counting on my bare-metal hypervisor. Particularly I am interested in the L3 cache misses for an intel i7 06_1Eh processor. There are two methods that should give me the same result, the non-architectural MEM_LOAD_RETIRED.L3_MISS performance event and the uncore UNC_l3_MISS.ANY performance event. I assign either of these events to the IA32_PERFEVTSEL0, set the USR, OS, and EN bits, or the MSR_UNCORE_PERFEVTSEL0 setting the EN bits. And then I set their respective enable bits in their respective global performance control MSRs. However when I do a back to back read of the performance monitor counter, the count value increases (No loads have been performed between the reads of the monitors). How do I check the number of L3 cache misses reliably? Does anyone know of any examples? I want to be able to check the counter back to back, show no increase in count, read >8MB addresses and check the counters again and see that the counter did register a L3 ca...
Cloud Computing Via Virtualization
By Urmit Hirapara3
Dear Friends, Now a Days Cloud Computing takes a lead in IT industry. We all Knows How Cloud Works.First We need to setup one server that creats main node or cluster (Master) and Others are Supporting Node.I have some idea about Infrastructure as a service via Ubuntu server. In IaaS we have some Actual Processors and Chunks of Hardware but Through Virtualization We can Create a Node. And Friend If You have any Idea About Clusters,Nodes and Virtual Server than You can Post Here. Now a days i m developing Cluster Monitoring System.
Cloud Computing Via Virtualization
By Urmit Hirapara2
Dear Friends, Now a Days Cloud Computing takes a lead in IT industry. We all Knows How Cloud Works.First We need to setup one server that creats main node or cluster (Master) and Others are Supporting Node.I have some idea about Infrastructure as a service via Ubuntu server. In IaaS we have some Actual Processors and Chunks of Hardware but Through Virtualization We can Create a Node. And Friend If You have any Idea About Clusters,Nodes and Virtual Server than You can Post Here. Now a days i m developing Cluster Monitoring System.
performance counter question
By heinerj1
Can rdpmc be used to read the uncore performance counters for an i7 processor? Or is the only way to read them through the MSR?
MSR-Bitmaps
By heinerj2
Having problems with the MSR bitmaps. I read the IA32_VMX_PROCBASED_CTLS MSR, set bit 28 and stored it into the vmcs's Primary proc-based VM-execution controls field. I then have the following structure in the vmcs header file: struct MSR_BITMAP{u64 MSR_READ_LO[128];u64 MSR_READ_HI[128];u64 MSR_WRITE_LO[128];u64 MSR_WRITE_HI[128];} __attribute__ (( aligned (4096) )); and in the vmcs.cI have the following code that should clear all bits in the MSR bitmap pointed to by the MSR_BITMAP address of the vmcs field so that no MSR read or write will cause a VM exit: struct MSR_BITMAP MSR_BITMAP1; unsigned long MSR_BITMAP_ADDR = (unsigned long) &MSR_BITMAP1;memset(&MSR_BITMAP1, 0, sizeof(MSR_BITMAP1)); //this should clear all bits in the bitmap forcing no MSRs to cause a VM exit__vmwrite (MSR_BITMAP_LO, (u32)MSR_BITMAP_ADDR);__vmwrite (MSR_BITMAP_HI, (u32)(MSR_BITMAP_ADDR >> 32)); In the VM i have the following code trying to read a MSR: rdmsrl(MSR_IA32_APIC_BASE_BSE, apic_base)...

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Contributeurs du forum

David Ott : ingénieur logiciel principal du groupe des solutions logicielles d’Intel, David travaille depuis quelques temps sur les différents aspects de l’informatique d’entreprise, y compris la virtualisation, l’efficacité énergétique et la sécurité. David possède une maîtrise et un doctorat en sciences informatiques de l’université de Caroline du Nord à Chapel Hill.

Hussam Mousa est ingénieur logiciel au centre des technologies d’optimisation des systèmes (SOTC) chez Intel. Il travaille sur l’analyse des performances de virtualisation, notamment sur les performances des E/S des applications d’entreprise. Il a publié plusieurs articles sur l’analyse des performances de virtualisation dans les conférences d’enseignement. Il a reçu son doctorat de l’université de Californie à Santa Barbara en 2010 et possède une licence de sciences de l’université américaine du Caire en 2002. Il travaille chez Intel depuis 2007.

Karthik Narayanan est ingénieur logiciel chez Intel, travaillant sur les applications d’entreprise et de gestion, les clusters et la haute disponibilité, l’informatique à la demande, native et virtualisée. Ses 4 années passées chez Intel ont été précédées par des expériences professionnelles dans des sociétés de génie logiciel de New York et d’Inde. Karthik a obtenu une licence d’ingénierie à l’université de Madras, en Inde, et sa maîtrise en sciences informatiques à l’université de Toledo.