Author's Blogs

Wellington and Austin: programming lots of cores
By James Reinders (Intel)Posted 04/03/20120
A couple of back-to-back opportunities to see great talks about harness lots of cores, and to give talks about programming options and why we do not need to give up on programmability in our quest for high performance.Wellington this week, Austin next week. Programming is not easy, and neither is...
Coarse-grained locks and Transactional Synchronization explained
By James Reinders (Intel)Posted 02/07/20123
Coarse-grained locks, and the importance of transactions, are key concepts that motivate why Intel Transactional Synchronization Extensions (TSX) is useful.  I’ll do my best to explain them in this blog. In my blog "Transactional Synchronization in Haswell," I describe new instructions (Intel TSX...
Transactional Synchronization in Haswell
By James Reinders (Intel)Posted 02/07/201212
We have released details of Intel® Transactional Synchronization Extensions (TSX) for the future multicore processor code-named “Haswell”. The updated specification (Intel® Architecture Instruction Set Extensions Programming Reference) can be downloaded. In this blog, I’ll introduce Intel TSX and...
OPEN CASCADE introduced parallelism into SALOME SMESH Module (using our tools)
By James Reinders (Intel)Posted 12/21/20110
OPEN CASCADE S.A.S and Intel Corporation software teams decided to join their efforts to introduce parallel calculations into Salome SMESH Module. They developed with the help of Intel® Parallel Studio XE. They wrote an article about it which can be downloaded (for free) from Parallelism_in_SMESH...
"Award Winning" Intel Parallel Studio XE
By James Reinders (Intel)Posted 11/23/20115
Intel Parallel Studio XE, in the category of "Best HPC software product or technology," was honored in the annual HPCwire Readers Choice Awards. The awards are an annual feature of the publication and constitute prestigious recognition from the high performance computing community. The awards wer...
quick chat about MIC architecture with Mike Dewar, NAG
By James Reinders (Intel)Posted 11/17/20113
I ran into Mike Dewar at SC11 today as the exhibition draws to a close.  Mike is the CTO of NAG Ltd. - a company we've had the good fortune to work with for years. NAG is one of a handful of companies that have been providing feedback on our Knights Ferry (prototype MIC architecture). Mike told m...
Seeing One TeraFlop/sec, the software side, and feeling a bit emotional
By James Reinders (Intel)Posted 11/17/20110
I've known this day was coming - but when I saw Knights Corner clearly sustaining a TeraFlop (DGEMM, wide range of block sizes) per second - I was surprised by my emotional reaction inside. Hard to describe; it was a good feeling. Tuesday November 15, 2011, we showed a Knights Corner co-processor...
Ready for 2X Moore's Law: Intel Cluster Studio XE
By James Reinders (Intel)Posted 11/08/20110
Today we introduced Intel® Cluster Studio XE, an exciting collection of powerful tools, for HPC programmers who use MPI along with other programming models to make the most of clusters and supercomputers. Intel Cluster Studio XE provides two substantial new capabilities to assist in hybrid progra...
Fortran is more popular than ever; Intel makes it FAST
By James Reinders (Intel)Posted 09/24/20112
Just this past week, a senior radio telescope astronomer told me about the shift from C++ back to Fortran in his corner of the world. It is all about efficiency. He believes this is a trend that will get stronger as we head to ExaFLOP scale machines at the end of this decade. I'm sure C++ has not...
Parallel Studio XE SP1: Extreme Computing is a journey to the future, not a detour
By James Reinders (Intel)Posted 09/15/20112
I am not a fan of detours. The challenge of scaling to extreme computing is a milestone on the road to every day computing. In Justin Rattner's keynote this morning at IDF, we got to see another example of how we make programs, for multicore processors, run on many-core processors. Andrzej Nowak ...