Intel® Developer Zone:
Intel ISA Extensions

Annunci
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

 
Argomento/Primo post Data di inserimento Risposte Ultimo Postordinamento crescente
Discussione normale Could intel somehow initiate migration/cleanup for x86 instruction set?
di htuh
Gio, 12/11/2009 - 16:13 0
di htuh
Mar, 12/01/2010 - 10:45
Discussione normale TSC Problem
di faball
Ven, 27/11/2009 - 02:52 0
di faball
Lun, 11/01/2010 - 09:36
Discussione normale mul instruction latency
di tthsqe
Sab, 09/01/2010 - 22:52 3
di Max Locktyukhin...
Sab, 09/01/2010 - 22:52
Discussione normale Debugging SSE/SSE2 ?
di gol
Gio, 24/12/2009 - 03:26 10
di gol
Mer, 06/01/2010 - 04:54
Discussione normale question on avx instruction encoding
di tthsqe
Ven, 01/01/2010 - 02:19 9
di mariaosawa
Ven, 01/01/2010 - 02:19
Discussione normale ow to calculate latency and throughput of instruction?
di maa1
Gio, 17/12/2009 - 10:32 2
di maa1
Gio, 17/12/2009 - 10:32
Discussione normale We need standardization of the x86 instruction set
di Agner
Sab, 05/12/2009 - 09:35 10
di Igor Levicki
Sab, 05/12/2009 - 09:35
Discussione normale VEX prefix and ymm state saving support
di yuhong2
Gio, 03/12/2009 - 23:19 1
di Brijender Bhart...
Ven, 04/12/2009 - 09:00
Discussione normale Illegal Instruction -- Intel SDE with AES instructions
di rksm
Mar, 01/12/2009 - 07:58 3
di Mark Charney (Intel)
Mar, 01/12/2009 - 07:58
Discussione normale How does address be mapped onto a memory bank
di zhangyihere
Mar, 01/12/2009 - 02:04 0
di zhangyihere
Mar, 01/12/2009 - 07:30
Discussione normale PTEST improvement?
di Matthias Kretz
Mar, 24/11/2009 - 00:59 1
di Max Locktyukhin...
Mar, 24/11/2009 - 00:59
Discussione normale Low rate on sse2 code
di maa1
Lun, 23/11/2009 - 11:39 0
di maa1
Lun, 23/11/2009 - 11:39
Discussione normale How many info could I get to estimate DRAM bandwidth?
di hchen229
Mar, 17/11/2009 - 08:17 1
di Roman Dementiev...
Mar, 17/11/2009 - 08:17
Discussione normale Understanding my Benchmarks
di Matthias Kretz
Mar, 10/11/2009 - 08:13 5
di Matthias Kretz
Mar, 10/11/2009 - 08:13
Discussione normale Why "subq" as allocate by ICC-v10.0 but not as prologue, but ICC-v11.0 uses "pushq" as prologue?
di srimks
Mer, 21/01/2009 - 01:10 3
di Sergey Maslov (...
Lun, 02/11/2009 - 22:18
Discussione normale sse4.2 instructions
di westmere
Ven, 01/05/2009 - 16:03 7
di Shih Kuo (Intel)
Lun, 02/11/2009 - 09:54
Discussione normale Opcode semantics
di matt.j
Gio, 13/08/2009 - 18:24 3
di c0d1f1ed
Lun, 02/11/2009 - 00:38
Discussione normale help on detecting stalls(identifying structural hazards) in assembly code
di ddmetro
Mer, 28/10/2009 - 10:18 1
di Tim Prince
Mer, 28/10/2009 - 10:18
Discussione normale is there a standard format in which we provide architecture specific information to a software
di ddmetro
Dom, 25/10/2009 - 16:24 0
di ddmetro
Dom, 25/10/2009 - 16:24
Discussione normale how to turn off out-of-order execution in Intel processor
di ddmetro
Dom, 25/10/2009 - 14:32 3
di ddmetro
Dom, 25/10/2009 - 14:32
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