MITE Micro-ops to IDQ

MITE Micro-ops to IDQ

Ritratto di Patrick Konsor (Intel)
TITLE: MITE Micro-ops to IDQ ISSUE_NAME: MITEUopsToIDQ DESCRIPTION:  Percentage of micro-ops delivered to the Instruction Decode Queue (IDQ) from the Micro Instruction Translation Engine (MITE), which is the unit that decodes instructions into micro-ops. Micro-ops can also be delivered from the Decoded Stream Buffer (DSB or Decoded Micro-op Cache) - a unit that caches micro-ops after they've been decoded by the MITE - as well as the Micro Sequence ROM - a unit that handles assists and stores micro-ops for instructions that cannot be decoded.   RELEVANCE: MITE has bottlenecks that can occur like Length Changing Prefix stalls (LCP) and decode stalls. The MITE also uses more power than the DSB. Because of this it is desirable to minimizing the percentage of micro-ops from the MITE. Additionally, transitioning from the DSB to the MITE causes a penalty, so it's ideal to minimize those transitions. EXAMPLE:   SOLUTION:   RELATED_SOURCES: DSBUopsToIDQ - Percentage of micro-ops delivered from the DSB. MSUopsToIDQ - Percentage of micro-ops delivered from MS ROM. DSB2MITE_SWITCHES.COUNT - Number of DSB to MITE switches. DSB2MITE_SWITCHES.PENALTY_CYCLES - Cost of DSB to MITE switches.
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