The following is a question received by Intel Software Network Support, followed by the response provided by our Application Engineers:
Q. Are the below assumptions correct regarding the increment/decrement operations on Intel processors?
1. Increment/decrement operations on 32-bit or less integer variables on a single 32-bit processor with no Hyper-Threading Technology are atomic.
2. On a processor with Hyper-Threading Technology or on a multi-processor system, the increment/decrement operations are NOT guaranteed to be executed atomicaly.
How about 64-bit processors?
An official Intel document which describes the atomic operations would be really welcomed!
A. The rules for atomic operations may be found in Chapter 7, Locked Atomic Operations, of the IA-32 Intel Architecture Software Developers Manual, Volume 3: System Programming Guide (http://developer.intel.com/design/Pentium4/documentation.htm). Here, it is guaranteed that simple loads or stores will be automatically atomic as long as the memory location is aligned on the appropriate boundary (16-bit boundary for 16-bit values, 32-bit boundary for 32-bit values, and so forth). In addition, simple loads or stores that are not aligned on the appropriate boundary are still guaranteed to be executed atomically if the 16, 32, or 64-bit values fit completely within a 32-byte cache line. Loads and stores that cross cache lines are not guaranteed to be executed atomically. In these cases, you can use the LOCK prefix to guarantee atomic operation of the simple load or store.
INC and DEC belong to the family of instructions that can read, modify, and write a data value in memory. Thus, their operation is not guarnateed to be atomic unless the LOCK prefix is used for these instructions (when referencing a location in memory). The XCHG instruction automatically causes the LOCK behavior to occur regardless of whether the prefix is used or not.
Message Edited by intel.software.network.support on 12-02-2005 08:48 PM