vmx-preemption timer inaccuracy (across vmx transitions)

vmx-preemption timer inaccuracy (across vmx transitions)

Hi,

From what I understand, the VMX-preemption timer should only decrement when in VMX non-root operations. I have been trying to use it as a way to measure cycle time in a VM, with respect to the running time of that VM. Hence, I do not want to include in my measurement the time spent in the VMM or the time to perform VM entries/exits. VMX-preemption timer seems like it could serve that purpose (with the granularity of the TSC to VMX-preemption timer ratio).

However, in my test, the VMX-preemption timer seems to also decrement while performing VM entry/exits.

My test:

a) from the VMM: read the VMX-preemption timer in the VMCS

b) VM enter

c) VM exit *immediately after VM enter* (eip set to the hlt instruction)

d) from the VMM: read the VMX-preemption timer in the VMCS (processor setup to save the VMX-preemption timer to VMCS on VM exit)

the difference between (d) and (a) should be zero or a very small value since the VMX-preemption timer should only be decrementing when executing in VMX non-root. However, after repeating this test consecutively for 200 times, what I get is a range of values from 70 - 140.  This seems to indicate that the VMX-preemption timer is decrementing while performing the VM entry/exit and not just while in non-root operations. There is no interrupts/exceptions being injected in between the VM enter and subsequent VM exit. Can someone confirm that this is the behavior of VMX-preemption timer and/or explain how one can get such large differences despite the fact that the VM spends almost no time in non-root operations.

I'm using Xeon E5520 2.2GHz with the TSC to VMX-preemption timer ratio of 5. I modified the Xen VMM to perform this test.

Thanks,

Mike

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Hi, Please refer to the erratum regarding the VMX-preemption timer. It suggests that VMX-preemption timer should not be used on this particular processor. Currently, there is no workaround.
Regards,
-Thai

Erratum URL:
http://www.intel.com/content/dam/www/public/us/en/documents/specificatio...

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