What are the reasons to issue machine clear signals. Do these signals relate to pipeline clears?
On Intel westmere, there are events breaking down the clear signals: MACHINE_CLEARS.CYCLES, MACHINE_CLEAR.MEM_ORDER, MACHINE_CLEARS.SMC. I understand that memory order violations and self-modifying code will flush the pipeline.
What else? It seems that the trend in event MACHINE_CLEARS.CYCLES does not agree with the trend in MEM_ORDER or SMC.