I am researching on multi-core scheduling algorithms, and need some information about Intel Xeon 5310 (Clovertown) processor. As you know, Clovertown is a two-package quad-core processor. Each package consists of a dual core processor. So, Could you tell me caches are inclusion or exclusion in Clovertwon?
I asked the question from Intel support centre, and found that all caches are inclusive. So, I have another question. Suppose block x is loaded to L1 cache of core0 in Clovertown (block x will be loaded to shared L2 cache). Then, the block is evicted from L1 of core0. (Therefore, block x will be evicted form shared L2). After a while, core1 accesses to block x. In this case, L2 cannot help core1 to retrieve block x. In the other words, inclusion has negative effect on thread affinity. Isn't it true?