# VSL Structure

The VSL component of Intel® MKL contains a set of generators to create general probability distributions, most commonly used in simulations, such as uniform, normal (Gaussian), exponential, or Poisson. Non-uniform distributions are generated using various transformation techniques applied to the output of a basic (pseudo-random, quasi-random, or non-deterministic) number generators.

To generate random numbers of a given probability distribution, you can either choose one of the available VSL BRNGs or register your own BRNG. To enhance their performance, all VSL BRNGs are highly optimized for various architectures of Intel® processors. Besides, VSL provides a number of different techniques for transforming uniformly distributed random numbers into a sequence of required distribution.

All VSL RNGs are of vector type. Unlike scalar type generators that return a successive random number, vector generators produce a vector of *n* successive random numbers of a given distribution with given parameters.

VSL is a thread-safe library, convenient for parallel computing, with a variety of configurations of parallel systems. A random stream is a notion in the RNG subcomponent of VSL. A mechanism of streams provides simultaneous generation of several random number sequences produced by one or more BRNGs, as well as splitting of the original sequence into several subsequences by the leapfrog and block-split methods. Several random streams are particularly useful not only in parallel applications but in sequential programs as well.

Optimization Notice |
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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 |