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  1. processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 60 ...

    https://software.intel.com/sites/default/files/managed/f3/f8/cpuinfo.txt

    ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm ...

  2. processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 42 ...

    https://software.intel.com/sites/default/files/forum/377784/proc-cpuinfo.txt

    ... pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon ...

  3. cache write back for pci device

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/393070

    May 29, 2013 ... Basically I confirmed what the SDM says about cache except that when I set both PAT and MTRR to write back, the linux kernel went to a fatal ...

  4. processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 63 ...

    https://software.intel.com/sites/default/files/managed/32/be/cpuinfo.txt

    ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm ...

  5. Monitoring PCIe Data for Xeon E5-2600

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/500900

    Feb 2, 2014 ... Some sub-regions of the IO hole address range will have an MTRR of .... the default mapping for regions not mapped by an MTRR to uncached.

  6. Is it possible to access RAM directly while the memory is cached?

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/419444

    Aug 20, 2013 ... Immediately, I modified the current core's MTRR to set the physical ... of MTRR because the correctness is verified by memory access timing.

  7. processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 62 ...

    https://software.intel.com/sites/default/files/managed/33/ba/cpuinfo.txt

    ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm ...

  8. processor : 0 vendor_id : AuthenticAMD cpu family : 21 model

    https://software.intel.com/sites/default/files/managed/5d/c8/cpuinfo.txt

    ... tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good  ...

  9. Cache Enabled/Disabled?

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/278571

    Apr 27, 2012 ... ... aL3cache miss. Myassumption is that ifthe MTRR and PAT are writeback and Iset the CD&NW bits of CR0 then all levels of cacheare disabled.

  10. Compiling gsl 1.15 with Intel 12.1

    https://software.intel.com/en-us/forums/intel-c-compiler/topic/279461

    Feb 29, 2012 ... ... pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs ...

  11. Intel(R) Inspector XE 2011 (build 131372) feedback tool Copyright ...

    https://software.intel.com/sites/default/files/48/6f/info.txt

    ... msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx pdpe1gb rdtscp lm constant_tsc ida nonstop_tsc  ...

  12. [Exception] Address: 0x00002b26051e9277 Code ...

    https://software.intel.com/sites/default/files/comment/1738706/crash-info.txt

    ... msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx pdpe1gb rdtscp lm constant_tsc ida nonstop_tsc  ...

  13. EPT write back memory type and Machine Check exception

    https://software.intel.com/en-us/forums/virtualization-software-development/topic/282254

    Aug 24, 2011 ... When setting up EPT paging structures, software should make sure the EPT memory-type in the EPT entry matches the MTRR value for the ...

  14. non-cached memory impact on platform power consumption

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/498425

    Dec 24, 2013 ... What is the impact of allocating non-cached memory by the driver but still using snoop enabled DMA to this memory region (as per MTRR or ...

  15. Cache-references and Cache-misses counters

    https://software.intel.com/en-us/forums/intel-performance-tuning-utility/topic/288159

    Aug 16, 2010 ... Using the linux /proc/mtrr i have configured all physical memory space to be uncachable.I have then ran 'perf stat myapp' and looked on the ...

  16. Poor cache performance on Tigerton quad-core

    https://software.intel.com/en-us/forums/intel-vtune-amplifier-xe/topic/304259

    Nov 2, 2007 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall nx lm ...

  17. Does VTune work with AMD Opteron processor?

    https://software.intel.com/en-us/forums/intel-vtune-amplifier-xe/topic/309160

    Feb 24, 2005 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall mmxext lm 3dnowext ...

  18. Write Combine Performance and Out of Order

    https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/518062

    Jul 13, 2014 ... The device driver set IO memory region using ioremap_wc (MTRR). This IO memory is the non prefetchable region. The PAT can be set with ...

  19. [Exception] Address: 0x00007f81c6308cc9 Code ...

    https://software.intel.com/sites/default/files/managed/b7/bb/vtune_crash.txt

    Jan 20, 2016 ... ... de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp ...

  20. gsl installation with intel compilers

    https://software.intel.com/en-us/forums/intel-c-compiler/topic/291743

    Feb 1, 2010 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm ...

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