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Part 5 of 5 - Performance analysis and events with Intel® VTune™ Amplifier XE

Part 5 of 5 - Performance analysis and events with Intel® VTune™ Amplifier XE. GUI and command line, setup and collection, hot spots, bandwidth, events & more.

Creato da admin Data ultimo aggiornamento 01/07/2015 - 16:05
Video

Episode 2.1 - Purpose of the MIC architecture

In this video episode 2.1 we will introduce Intel Xeon Phi coprocessors based on the Intel Many Integrated Core, or MIC, architecture and will cover some of the specifics of hardware implementation

Creato da admin Data ultimo aggiornamento 01/07/2015 - 15:50
Video

Respect programming models – manage Intel Xeon Phi’s in your Clusters for enhanced user experience

HPC cluster programming model number 1 has been MPI for the past 10 or more years.

Creato da admin Data ultimo aggiornamento 15/05/2015 - 08:44
Article

OpenCL* Design and Programming Guide for the Intel® Xeon Phi™ Coprocessor

About this document
Creato da admin Data ultimo aggiornamento 12/05/2015 - 12:33
Article

面向英特尔® 至强融核™ 协处理器的 OpenCL* 设计和编程指南

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Creato da admin Data ultimo aggiornamento 12/05/2015 - 12:33
Video

Episode 2.2 - Details of Intel MIC Architecture

In this video we will discuss the general properties of the Intel MIC architecture in detail, and then focus on vector instruction support.

Table of Contents:

Creato da admin Data ultimo aggiornamento 06/05/2015 - 19:46
Video

Episode 3.9 - File I/O in MPI Applications on Coprocessors

In this video we will talk about running your distributed MPI calculation, and later about file I/O functionality available on Intel Xeon Phi coprocessors.

Creato da admin Data ultimo aggiornamento 06/05/2015 - 16:25
Video

Episode 3.8 - Heterogeneous Programming with Coprocessors using MPI

In this episode 3.8 we will be talking about using multiple coprocessors in a cluster environment.

Creato da admin Data ultimo aggiornamento 06/05/2015 - 16:25
Video

Episode 3.7 - Asynchronous Offload

Next in this episode 3.7 we will look at how to overlap communication of data with computation on the coprocessor and CPU at the same time in the explicit offload model.

Creato da admin Data ultimo aggiornamento 06/05/2015 - 16:25
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