Part 5 of 5 - Performance analysis and events with Intel® VTune™ Amplifier XE. GUI and command line, setup and collection, hot spots, bandwidth, events & more.
In this video episode 2.1 we will introduce Intel Xeon Phi coprocessors based on the Intel Many Integrated Core, or MIC, architecture and will cover some of the specifics of hardware implementation
HPC cluster programming model number 1 has been MPI for the past 10 or more years.
In this video we will discuss the general properties of the Intel MIC architecture in detail, and then focus on vector instruction support.
Table of Contents:
In this video we will talk about running your distributed MPI calculation, and later about file I/O functionality available on Intel Xeon Phi coprocessors.
In this episode 3.8 we will be talking about using multiple coprocessors in a cluster environment.
Next in this episode 3.7 we will look at how to overlap communication of data with computation on the coprocessor and CPU at the same time in the explicit offload model.
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