Filtri

Article

Replay of sessions talking about programming for Intel® Xeon Phi™ Coprocessors

This page contains replays of 5 sessions covering a variety of topics as listed below:

Creato da admin Data ultimo aggiornamento 02/02/2016 - 12:18
Article

Memory Management Optimizations on the Intel® Xeon Phi™ Coprocessor Using Abstract Vector Register Selection, _mm_malloc, mmap, and Prefetching

This article examines memory management performance optimization on the Intel® Xeon Phi™ using a non-library version of DGEMM. The performance optimizations incorporate dynamic storage allocation, high-level vector register management, and data prefetching. Code sample included.
Creato da Steve H. (Intel) Data ultimo aggiornamento 13/01/2016 - 06:52
Article

Programming for Multicore and Many-core Products including Intel® Xeon® processors and Intel® Xeon Phi™ X100 Product Family coprocessors

Programming for Multicore and Many-core Products including Intel® Xeon® processors and Intel® Xeon Phi™ X100 Product Family coprocessors (including language extensions for offloading to Intel® Xeo
Creato da James Reinders (Intel) Data ultimo aggiornamento 15/12/2015 - 13:31
Blog post

C-States, P-States, where the heck are those T-States?

I had an interesting question come across my desk a few days ago: “Is it still worthwhile to understand T-states?” My first response was to think, “Huh? What the heck is a T-state?”

Creato da Taylor K. (Intel) Data ultimo aggiornamento 11/12/2015 - 14:39
Blog post

The Chronicles of Phi - part 1 The Hyper-Thread Phalanx

The term phalanx is derived from a military formation used by the ancient Greeks and Romans. The formation generally involved soldiers lining up shoulder to shoulder, shield to shield multiple rows deep. The formation would advance in unison becoming “an irresistible force.” I use the term Hyper-Thread Phalanx to refer to the Hyper-Thread siblings of a core being aligned shoulder-to-shoulder and...
Creato da jimdempseyatthecove Data ultimo aggiornamento 25/11/2015 - 16:59
Blog post

The Chronicles of Phi - part 3 Hyper-Thread Phalanx – tiled_HT1 continued

The prior part (2) of this blog provided a header and set of function that

Creato da jimdempseyatthecove Data ultimo aggiornamento 25/11/2015 - 16:59
Article

Running R with Support for Intel® Xeon Phi™ Coprocessors

Introduction
Creato da admin Data ultimo aggiornamento 02/11/2015 - 16:45
Video

"Correct" to "Correct and Efficient": A Case Study with Hydro2D

Upon completion of this webinar, you will be familiar with how a given physical process be simulated on a computer efficiently.

Creato da admin Data ultimo aggiornamento 13/10/2015 - 11:57
Blog post

Prominent features of the Intel® Manycore Platform Software Stack (Intel® MPSS) version 3.6

The Intel® Manycore Platform Software Stack (Intel® MPSS) version 3.6 was released on October 1st, 2015. This page lists the prominent features in this release.
Creato da Ignacio H. (Intel) Data ultimo aggiornamento 12/10/2015 - 15:52
Article

Porting and Tuning of Lattice QCD & MPI-HMMER for Intel® Xeon® Processors & Intel® Xeon Phi™ Coprocessors

The Intel® Xeon Phi architecture from Intel Corporation features parallelism at the level of many x86-based cores, multiple threads per core, and vector processing units.

Creato da Frances Roth (Intel) Data ultimo aggiornamento 23/09/2015 - 13:39
Per informazioni più dettagliate sulle ottimizzazioni basate su compilatore, vedere il nostro Avviso sull'ottimizzazione.