This page contains replays of 5 sessions covering a variety of topics as listed below:
Memory Management Optimizations on the Intel® Xeon Phi™ Coprocessor Using Abstract Vector Register Selection, _mm_malloc, mmap, and PrefetchingThis article examines memory management performance optimization on the Intel® Xeon Phi™ using a non-library version of DGEMM. The performance optimizations incorporate dynamic storage allocation, high-level vector register management, and data prefetching. Code sample included.
Programming for Multicore and Many-core Products including Intel® Xeon® processors and Intel® Xeon Phi™ X100 Product Family coprocessorsProgramming for Multicore and Many-core Products including Intel® Xeon® processors and Intel® Xeon Phi™ X100 Product Family coprocessors (including language extensions for offloading to Intel® Xeo
I had an interesting question come across my desk a few days ago: “Is it still worthwhile to understand T-states?” My first response was to think, “Huh? What the heck is a T-state?”
The prior part (2) of this blog provided a header and set of function that
Upon completion of this webinar, you will be familiar with how a given physical process be simulated on a computer efficiently.
Porting and Tuning of Lattice QCD & MPI-HMMER for Intel® Xeon® Processors & Intel® Xeon Phi™ Coprocessors
The Intel® Xeon Phi architecture from Intel Corporation features parallelism at the level of many x86-based cores, multiple threads per core, and vector processing units.