AES New Instructions
- Intel® AES New Instructions (Intel® AES-NI)
Panoramica su Intel® AES-NI, un nuovo insieme di istruzioni di crittografia che migliora l'algoritmo Advanced Encryption Standard (AES) e accelera la crittografia dei dati.
- Proteggere l'azienda con Intel® AES-NI
Scoprite perché la crittografia è un argomento di primo piano nel mercato di oggi, specialmente per le aziende.
- Intel® Advanced Encryption Standard Instructions (AES-NI)
Descrizione delle sei nuove istruzioni che costituiscono l'insieme di istruzioni AES-NI ed eseguono numerose parti ad elaborazione intensiva dell'algoritmo AES.
Generatore digitale di numeri casuali
- Bull Mountain è il nome che Intel ha assegnato alla sua ultima istruzione RdRand dell'architettura Intel® 64 e alla relativa implementazione hardware del generatore digitale di numeri casuali (DRNG) su cui si basa tale istruzione. Bull Mountain offre una soluzione RNG basata su processore dalla qualità e prestazioni elevate, altamente disponibile e sicura.
Estensioni dei set di istruzioni dell'architettura Intel
- Intel® Memory Protection Extensions (Intel® MPX) è un nome per le estensioni dell'architettura Intel progettate per aumentare la robustezza del software
- Intel® Software Guard Extensions (Intel® SGX) è un nome per le estensioni dell'architettura Intel progettate per aumentare la sicurezza del software attraverso un meccanismo a “sandbox inversa”
- Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) sono un insieme di sette istruzioni basate su Intel® Streaming SIMD Extensions (Intel® SSE) che sono usate insieme per accelerare le prestazioni di SHA-1 e SHA-256 sui processori basati sull'architettura Intel
Jump start your software development for the soon to be released Intel® Core™2 processor with vPro™ technology (codenamed: McCreary). Get an overview of the Intel Active Management Technology (Intel AMT) and all new features in the Intel AMT 4.0/5.0. Register for this free event and take advantag...
Reducing Data Center Energy Consumption - A summary of strategies used by CERN, the world's largest physics laboratory
To deploy massive new computing resources without exceeding the thermal limits of its 35-year-old data center, CERN is taking a comprehensive approach to improving energy efficiency. This paper outlines CERN's key strategies, including a move to the latest Intelr Xeonr processors that are helping...
Di Ajith Illendula (Intel)Pubblicato il 04/13/20110
Intel® Active Management Technology Use Case #12: Fast Call for Help User Fast Call for Help aka Client Initiated Remote Access (CIRA) feature of Intel® Active Management Technology (Intel® AMT) allows Intel® vPro™ technology platforms to initiate a secured connection to a gateway server residing...
Di Ajith Illendula (Intel)Pubblicato il 04/13/20110
Intel® Active Management Technology Use Case #12:Fast Call for Help Fast Call for Help aka Client Initiated Remote Access (CIRA) feature of Intel® Active Management Technology (Intel® AMT) allows Intel® vPro™ technology platforms to initiate a secured connection to a gateway server residing in th...
Tecnologia Intel® Virtualization
- Descrizione tecnica dell'hardware di virtualizzazione
La tecnologia Intel Virtualization fornisce strumenti hardware completi per accelerare le prestazioni del software di virtualizzazione, migliorare i tempi di risposta delle applicazioni e offrire una maggiore affidabilità, sicurezza e flessibilità.
- Virtualizzazione: al servizio dello sviluppatore
Più gli sviluppatori usano la virtualizzazione e più scoprono nuovi modi per utilizzarla. Scoprite che cosa vi state perdendo e come la virtualizzazione può aiutarvi a ottenere di più.
- Tecnologia Intel® Virtualization: animazione Flash*
Questa animazione offre una descrizione generale della tecnologia Intel® Virtualization che è una tecnica tramite cui le risorse hardware possono essere estratte, suddivise e quindi condivise tra più ambienti di sistemi operativi in esecuzione simultanea.
- Tecnologia Intel® Virtualization: best practice per i fornitori di software
Questa serie di articoli serve ai fornitori di software come guida per personalizzare le applicazioni per l'uso con la tecnologia Intel Virtualization.
During vmlaunch/vmresume, several checks are performed on the guest state area. I was wondering if anyone else had noticed that Guest RSP field is never checked for a non-canonical address. The virtualization spec talks about such checks for Guest RIP or GDTR or IDTR. I was wondering why this check was not done for the Guest RSP?
Di Yogi D.1
Hi. I am writing a small OS-agnostic hypervisor as a teaching tool for my students. The hypervisor code is loaded by the code I embed in a custom MBR on the boot device when the system boots. The hypervisor code switches to 32-bit proected mode and then IA32e (64-bit mode). It then sets up the hypevisor, EPT to protect the hypervisor from the guests, and launches a 16-bit "unrestricted" big real-mode (or unreal mode) guest. All this is working perfectly. The guest can make BIOS calls. The hypervisor writes directly to the video buffer in order to provide debugging/status info. The hypervisor is setup to VMexit minimally (e.g., I/O, APIC, MSRs, etc. are not monitored -- yet). When the real-mode guest causes EPT violations, issues CPUID, etc. these cause VMExits as expected and the hypervisor handles them and resumes the guests. When the 16-bit guest issues an INIT IPI to itself using the APIC, I run into an infinite VMExit situation that my hypervisor cannot seem to recover ...
Di Tyler T.0
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Di Tracy Camp1
I'm aware that software can check the IA32_VMX_EPT_VPID_CAP MSR to determine if the EPT table supports access and dirty bits... However I would like to know how to identify a processor before I've purchased it that has this support. This is a common frustration I have with Intel parts - minor features vary quite a bit and don't seem to necissarily 'stick' in a linear progression of CPUID values due to various market differentiations. Most of the time it doesn't matter too much, since most features are just an optimization for something that doesn't need to be implemented in software, however in this particular case, I'm not sure how to 'emulate' the lack of an accessed and dirty bit in the EPT tables of earlier EPT implementations in software.
Di Hitesh Prajapati1
Dear Sir/Madam, We have intel 10GbE Network Adapter X540-T2. Please guide me for the virtualization testing software for the adapter. I am new to this forum, also guide me that is this correct forum for the 10GbE network Adapter X540-T2. Reply me as early as possible. Thanks in advacne.
Di Ralf H.1
Hi, we're currently working in a project that involves extending the KVM hypervisor. While running the VM, we sometimes get EPT violations that shouldn't be possible from our understanding of the Intel documents. The scenario is as follow (we use Intel VT with EPT enabled):All guest paging structures (i.e., the paging structures _inside_ the VM) are set to non-writable on the last EPT level. In other words, whenever the guest OS writes to a guest paging structure (e.g. to map/free a page), this triggers an EPT violation. Now, "occasionally" the following happens:The VM performs a normal read operation somewhere in memory (doesn't seem to matter where). This then yields an EPT violation and bit 0, bit 1, and bit 7 are set in the exit qualification field, bit 8 is cleared. According to the Intel specification (Table 27-7), this means that the EPT violation was caused by the MMU setting the dirty or accessed bit in the guest paging structures. At first, this makes sense since these ar...
Rather than force a user to abruptly break away from routines that have become easy to perform, I think it might be a good idea to run Windows 7 in a virtual environment on the new platform; provided it is possible to hotkey from the new work environment to the old, and back to the new in a New York minute. My interest in this came about when after changing from an old fashion notebook to an Ultraboook with a Touch screen I discovered the Start menu has changed, of course. Also, I realized that using a slow browser on a fast platform doesn’t make sense, so I left behind my beloved IE8 with iGoogle homepage and changed to speedy Google Chrome. Then I found myself wondering how to save Favorites, block pop-ups, establish and maintain trust relations, all things I had become somewhat familiar with doing, and now have to consciously think about again. I am looking forward to making greater use of audio and video processing capabilities in the new 64-bit environment. Since A/V file...
Di Michael L.1
Hi, From what I understand, the VMX-preemption timer should only decrement when in VMX non-root operations. I have been trying to use it as a way to measure cycle time in a VM, with respect to the running time of that VM. Hence, I do not want to include in my measurement the time spent in the VMM or the time to perform VM entries/exits. VMX-preemption timer seems like it could serve that purpose (with the granularity of the TSC to VMX-preemption timer ratio). However, in my test, the VMX-preemption timer seems to also decrement while performing VM entry/exits. My test: a) from the VMM: read the VMX-preemption timer in the VMCS b) VM enter c) VM exit *immediately after VM enter* (eip set to the hlt instruction) d) from the VMM: read the VMX-preemption timer in the VMCS (processor setup to save the VMX-preemption timer to VMCS on VM exit) the difference between (d) and (a) should be zero or a very small value since the VMX-preemption timer should only be decrementing when executing i...