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Estensioni dei set di istruzioni dell'architettura Intel - Now with Intel AMT certificate activation
Di ylian-saint-hilaire (Intel)Pubblicato il 08/15/20130
I just added certificate based Intel AMT cloud activation support (TLS-PKI) in that works behind NAT’s and HTTP proxies, uses a reusable USB key and makes use of Intel AMT one-time-password (OTP) for improved security. Ok, let’s back up a little. Computers with Intel AMT need t...
The future of authentication and transactions over the web (Part 1)
Di Jose DamicoPubblicato il 06/18/20130
Banks and the payment industry have realized long ago that knowledge is not enough to confirm money transactions through the web. Even apparently strong techniques such as tokens and smartcards have been facing the challenge to deal with Malware and Hacker attacks. Then, to avoid blind signing, i...
IDC White Paper: Running Mission-Critical Workloads on Enterprise Linux x86 Servers
Di ROBERT M.Pubblicato il 05/06/20130
This IDC white paper, sponsored by Intel,  examines the growth of mission-critical workloads being hosted on x86 servers based on the Intel Xeon E7 series of processors running enterprise Linux operating systems. It looks at the way in which x86 servers are taking on more demanding workloads, inc...
Intel® Identity Protection Technology with PKI - Technology Overview
Di Jeff Kataoka (Intel)Pubblicato il 03/19/20130
Corporate enterprise, government entities, healtcare and more are looking to add additional security to protect access to their network and business information. Intel® Identity Protection Technology on the latest PCs with Intel® Core® vPro™ processor can be combined with authentication security ...
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Tecnologia Intel® Virtualization

How to Take Advantage of the Virtualization `Appliance' Model in the Digital Home
Di Pubblicato il 09/15/20110
Challenge Benefit from the emerging ‘appliance’ model in Digital Home virtualization. An exciting usage model for Intel® Virtualization Technology on desktops and laptops is to create appliances. With Intel Virtualization Technology, one can take the functions of a stand-alone firewall applianc...
Expand Digital Home Functionality with VT
Di Pubblicato il 09/15/20110
Challenge Use Intel® Virtualization Technology in conjunction with other technologies to improve the Digital Home experience. The advent of Intel Virtualization Technology corresponds to another, even more significant hardware transition: multi-core processing. These two technologies complement...
Digital Home Security with VT
Di Pubblicato il 09/15/20110
Challenge Improve security in the Digital Home by means of virtualization. As powerful entertainment PCs take over more functionality in the Digital Home, it will become more important than ever to secure these platforms. This necessity is even more pronounced in those cases where the same PC b...
Hide Hardware Complexity
Di Pubblicato il 09/15/20110
Challenge Hide the complexity of hardware from the operating system. Future microprocessors will need several levels of virtualization. For example, as shown in the figure below, virtualization is needed to hide the complexity of the hardware from the overlying software. The OS kernel and the s...
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EPT cause triple fault
Di Mingbo Z.4
Hi all, I am writing a simple runtime hypervisor, like hyperdbg, bluepill. At first it works fine. But when I enable EPT, the vm exits with triple fault (Exit reason 2). and the guest RIP was at the fist instruction in non-root mode after vmlaunch. There is no ept violation. I did some 1:1 direct mapping, since no ept violation, that would be no use at all. wired thing is, the same code will run on VMware virtual machine. My PC is Core i7, and I disabled multicore. and I use serial port with windbg.  I am confused, which instruction caused this triple fault? I change the first line of non-root mode to "mov edi, edi", still the same triple fault.    Best regards, Mingbo
EPT Violation On a PTE free
Di Saptarshi S.2
 Hi All,        Is it possible to configure EPT Entries or VMCS such that whenever a guest frees a page the host can instantaneously become aware of this. I have checked out the intel software developer manual 3B. But the closest I could  get is by causing a write violation in the EPT paging structure. But again, it did not seem proper as such writing violation can arise because of many other reasons as well. Besides, the whole performance of EPT would be destroyed if the guest does cache-writethrough.      I was testing this stuff with KVM and I could see that the host is not aware of  deallocations that  take place in the guest after allocations. Regards Saptarshi Sen        
Ambiguity with CR3-store/load exiting settings
Di Eugene K.2
I have Intel(R) Core(TM) i5-2500 CPU. RDMSR on IA32_VMX_PROCBASED_CTLS MSR gives allowed-0 settings 0x0401E172, allowed-1 settings 0xFFF9FFFE. This means bits 15 (CR3-load exiting) and 16 (CR3-store exiting) of Primary Processor-Based VM-Execution Controls must be 1. However I can set them to zero and no any invalid VM entries happen. Why? CPU details: processor       : 0vendor_id       : GenuineIntelcpu family      : 6model           : 42model name      : Intel(R) Core(TM) i5-2500 CPU @ 3.30GHzstepping        : 7microcode       : 0x26cpu MHz         : 1600.000cache size      : 6144 KBphysical id     : 0siblings        : 4core id         : 0cpu cores       : 4apicid          : 0initial apicid  : 0fpu             : yesfpu_exception   : yescpuid level     : 13wp              : yesflags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl...
Intel VT-x and VT-d for app development
Di Muhammad Khawar N.1
Hello, all! First some background on the situation:So, I'm going to be buying a new laptop soon, and one of my priorities is to do Windows Phone and Android app development on it. I don't play games, etc. so a high-end graphic chip is not my requirement. I need to run CPU-intensive simulation software like MATLAB occasionally so I need a good processor. Considering my budget and requirement and availability in my country; I've narrowed it down to two machines. An HP ProBook (which has an i7-3632QM processor + 8GB RAM), and an HP Pavilion (which has an i7-4702MQ + 4GB RAM). Now for the problem. Since I'll be doing app development, a good testing procedure is to test it on an emulator, for phone WP8 and Android... To run the emulators smoothly it is required that the processor support Intel Virtualization, and SLAT. Both processors do have Virtualization, but there is something called VT-d which is there for the Ivy Bridge but not the Haswell chip.  My questions are:1. Do I need VT-d ...
VT-d hardware support on chipset Z87 (DH82Z87)
Di Bogdan B.5
There seem to be some inconsistency on ARK product reference site: This document Compatibility with Intel® Virtualization Technology (Intel® VT) ( specifies that chipset Z87 (DH82Z87) supports VT-d:   The following Intel® Desktop Boards support Intel VT with Directed I/O:   ChipsetDesktop Board H87, Q87, Z87 - DH87MC, DH87RL, DQ87PG, DZ87KLT-75K and the chipset product page here says:   "Intel® Virtualization Technology for Directed I/O (VT-d) ‡ No". Please confirm if this chipset supports this virtualization feature. Thanks,Biv 
VT-d programming
Di Yogi D.2
I am trying to expriment with DMA remapping using VT-d.  By reading the VT-d spec, I know how to setup the remapping tables.  However, I don't know how to locate the register that will receive the base address of the remapping table hierarchy. Reading the spec for my processor, I see there is a Root-Entry Table Address Register ( RTADDR_REG) at offset 20–27h.  But what is the base of this "block" ( the spec says this is PEG/DMI VT-d Remapping Engine Register Address Map). Can anyone help me find this in the documentation somehwhere?  Thanks!
DPDK Question
Di Alexey I.1
Hi to everyone! A couple of questions about DPDK: 1. Can Intel DPDK work with double tagged ethernet frames? To read frame with 2 tags and to write frame to the wire with two tags (QinQ technology) 2. Can Intel DPDK read and write MPLS tags?
UnDocumented MSR's
Di Matthew K.2
I have come accross BIOS code that reads/writes an MSR ECX = 0x2e0.  I have scanned through all of the Intel documentation and cant find anything about this MSR The codes is executed on a CORE i7 3820qm Thanks Matt
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