Intel® Developer Zone:
Sicurezza e crittografia

AES New Instructions

Generatore digitale di numeri casuali

Estensioni dei set di istruzioni dell'architettura Intel

Intel® Identity Protection Technology with PKI - Technology Overview
Di Jeff Kataoka (Intel)Pubblicato il 03/19/20130
Corporate enterprise, government entities, healtcare and more are looking to add additional security to protect access to their network and business information. Intel® Identity Protection Technology on the latest PCs with Intel® Core® vPro™ processor can be combined with authentication security ...
Deeper Levels of Security with Intel® Identity Protection Technology - White paper
Di Jeff Kataoka (Intel)Pubblicato il 02/26/20131
White Paper: Deeper Levels of Security with Intel® Identity Protection Technology With the latest release in 2012 of Intel® Identity Protection Technology (Intel® IPT) introduced additional capabilities beyond the initial one-time password (OTP) solutions embedded in silicon and provided an exten...
Technology Brief: Intel® Identity Protection Technology ( Intel® IPT )
Di Jeff Kataoka (Intel)Pubblicato il 02/22/20130
Safeguard Sensitive Information with Intel® Identity Protection Technology ( Intel® IPT ) Guarding personal identities and online accounts has become a major concern for consumers, business, government and institution as the threat from hackers and malware grows.  Creating a simple, strong and se...
Developing secured embedded applications using Intel® System Studio
Di sukruth-v (Intel)Pubblicato il 02/12/20130
ntel® Static Analysis tool is capable of detecting around 250 different types of error conditions and can also detect race conditions resulting from misuse of parallel programming frameworks such as OpenMP* and Intel® Cilk™ Plus.
Iscriversi a Articoli Intel Developer Zone
Nessun contenuto trovato
Iscriversi a Blog Intel® Developer Zone
Nessun contenuto trovato
Iscriversi a Forum
Nessun contenuto trovato

Tecnologia Intel® Virtualization

Digital Home Security with VT
Di Pubblicato il 09/15/20110
Challenge Improve security in the Digital Home by means of virtualization. As powerful entertainment PCs take over more functionality in the Digital Home, it will become more important than ever to secure these platforms. This necessity is even more pronounced in those cases where the same PC b...
Hide Hardware Complexity
Di Pubblicato il 09/15/20110
Challenge Hide the complexity of hardware from the operating system. Future microprocessors will need several levels of virtualization. For example, as shown in the figure below, virtualization is needed to hide the complexity of the hardware from the overlying software. The OS kernel and the s...
Optimizing DirectX* 8.0 Vertex Shaders
Di Pubblicato il 09/09/20110
Optimizing DirectX* 8.0 Vertex Shaders Once again, welcome back to Maximum FPS! This month Ronen Zohar will provide us with a thorough understanding of how to take advantage of vertex shaders on Intel processors. Ronen is an Intel engineering manager from Haifa, Israel, and has worked closely wit...
Energy Efficiency of Virtual Machines
Di Abhishek Agrawal (Intel)Pubblicato il 06/24/20110
Designing low power virtualization solutions has become very important for extending the battery life of mobile systems. This paper reports the power profile of leading desktop virtualization solutions under idle and workload conditions.
Iscriversi a Articoli Intel Developer Zone
Nessun contenuto trovato
Iscriversi a Blog Intel® Developer Zone
VT-d hardware support on chipset Z87 (DH82Z87)
Di Bogdan B.5
There seem to be some inconsistency on ARK product reference site: This document Compatibility with Intel® Virtualization Technology (Intel® VT) (http://www.intel.com/support/motherboards/desktop/sb/CS-030922.htm) specifies that chipset Z87 (DH82Z87) supports VT-d:   The following Intel® Desktop Boards support Intel VT with Directed I/O:   ChipsetDesktop Board H87, Q87, Z87 - DH87MC, DH87RL, DQ87PG, DZ87KLT-75K and the chipset product page here http://ark.intel.com/products/75013/Intel-DH82Z87-PCH says:   "Intel® Virtualization Technology for Directed I/O (VT-d) ‡ No". Please confirm if this chipset supports this virtualization feature. Thanks,Biv 
VT-d programming
Di Yogi D.2
I am trying to expriment with DMA remapping using VT-d.  By reading the VT-d spec, I know how to setup the remapping tables.  However, I don't know how to locate the register that will receive the base address of the remapping table hierarchy. Reading the spec for my processor, I see there is a Root-Entry Table Address Register ( RTADDR_REG) at offset 20–27h.  But what is the base of this "block" ( the spec says this is PEG/DMI VT-d Remapping Engine Register Address Map). Can anyone help me find this in the documentation somehwhere?  Thanks!
DPDK Question
Di Alexey I.1
Hi to everyone! A couple of questions about DPDK: 1. Can Intel DPDK work with double tagged ethernet frames? To read frame with 2 tags and to write frame to the wire with two tags (QinQ technology) 2. Can Intel DPDK read and write MPLS tags?
UnDocumented MSR's
Di Matthew K.2
I have come accross BIOS code that reads/writes an MSR ECX = 0x2e0.  I have scanned through all of the Intel documentation and cant find anything about this MSR The codes is executed on a CORE i7 3820qm Thanks Matt
Processor Delays with Locking in multi-core VMs
Di Penny Svenkeson1
Hi all, In our hypervisor implementation, we can have multiple cores assigned to a single VM.  In the multi-core VM configuration, we are seeing longer delays under virtualization for cores getting locks (even when there is no contention for the lock cell). If a core (or thread) has a guest cache line resident and takes a VMEXIT for some reason and another core want to get ownership of the guest cache line (for atomic operation), does the 2nd core have to wait for the VMRESUME on the first core before getting ownership? Are there any other reasons that would prevent a core from completing an atomic operation if other cores are in a VMEXIT condition? Core1 has cache line A Core1 takes a VMEXIT for timer interrupt Core2 tries a sync_fetch_and_add to cache line A    <-- get ownership here Core1 does a VMRESUME                                     <-- or wait till here for ownership Thanks for any insight. Penny
Cross Compiling for Windows from Linux
Di jrm@exa.com0
Not sure what forum would be most appropriate for this question, but this seemed close at least....kindly advise if there's a better place! For many years my company has been interested in the availability of cross compilation for Windows from Linux.   Our primary development environment is Linux, and the various approaches to getting linux buildable software to build on windows involve various levels of pain and suffering of one sort or another.   Being able to create native windows binaries without having to duplicate development environments would be a real benefit.   Some level of capability in this regard has been available via the MinGW tools for at least a decade, and we used it for a time, but limitations such as inability to debug with ordinary windows tools were too much of a hinderance.   Since we believe the claim that ICC is really the same compiler on Windows and Linux, it seems like it would be very straight-forward to create a Linux version of the compiler able to cr...
Trouble with 16-bit guest and SMM interaction
Di Yogi D.1
I am writing a thin hypervisor that allows 16-bit mode guests.  The system boots into my 16-bit boot code which sets up 32-bit protected mode with identty mapped pages, then enables IA-32e compatibility mode and then switches into IA32e mode (64-bit).  In this mode, the software sets up a hypervisor to allow unrestricted guests (this includes setting up EPT with proper caching controls refecting the cache setup via MTRRs).  Then the software launches a 16-bit guest that runs well -- making BIOS calls for I/O services etc.  All this is working quite well. However, I noticed a small discrepency in behavior when I press the power button.  Before the 16-bit guest is launched, the system immediately shuts down when the power button is pushed.  This also happens when the host mode is active (i.e., my code is processing a VM Exit).  However, when the 16-bit mode guest is active, pushing the power button causes the machine to hang -- even the VM preemption timer does not cause a VM Exit. Be...
intel vt-d for hvm
Di Tommy F.1
Hello can someone explain why intel vt-d is required for HVM ( fully virtualized VM) and not for Para-virtualized VMs. I know that in the pci-passthrough, the VM has control of the PCI. so the PCI needs to do DMA access to the VM memory, but as this is not possible, the PCI will tell the IOMMU about the virtual address, which will be converted to the physcial address in RAM, which corresponds to the VM memory. But what happens in case of Para-virtualization VM?
Iscriversi a Forum
Nessun contenuto trovato