MIC

Submissions open: High Performance Parallelism Gems

We have all had our little discoveries and triumphs in identifying new and innovative approaches that increased the performance of our applications. Occasionally we find something more, something that could also help others, an innovative gem. You now have an opportunity to broadcast your successes more widely to the benefit of our community. You are invited to submit a proposal to a contribution-based book, working title, “High Performance Parallelism Gems – Successful Approaches for Multicore and Many-core Programming” that will focus on practical techniques for Intel® Xeon® processor and Intel® Xeon Phi™ coprocessor parallel computing. Submissions are due by May 29, 2014.

Power Management: So what is this policy thing?

Unlike a lot of previous recent blogs, this series is about power management in general. At the very end of the series, I’ll write specifically about the Intel® Xeon Phi™ coprocessor.

I have talked incessantly over the years about power states (e.g. P-states and C-states), and how the processor transitions from one state to another. For a list of previous blogs in this series, and well as other related blogs on power and power management, see the article at [List0]. But I have left out an important component of power management, namely the policy.

Performance BKMs: Introduction and Super-secret Intel Tools

At SC13 (Super Computing 2013)*, someone commented that Intel seems to have some super-secret set of tricks in its pocket, allowing us to optimize “far beyond those of mortal man”+. We don’t really have any super-secret tricks. Even if we did, we wouldn’t use them. We want mortal man (you) to be able to reproduce whatever we do. It is also in our business interest to insure that you can optimize on Intel hardware to the fullest extent possible.

Resource Guide for People Investigating the Intel® Xeon Phi™ Coprocessor

This article identifies resources for anyone investigating the value to their organization of the Intel® Xeon Phi™ coprocessor, which is based on the Intel® Many Integrated Core (Intel® MIC) architecture. It is one of three such guides, each for people in one of the following specific roles:

  • Sviluppatori
  • Professori
  • Studenti
  • Linux*
  • Microsoft Windows* (XP, Vista, 7)
  • Microsoft Windows* 8.x
  • C/C++
  • Fortran
  • Avanzato
  • server
  • Parallel Programming
  • Taylor Kidd
  • Intel Xeon Phi Coprocessor
  • MIC
  • Knights Corner
  • manycore
  • Many Core
  • KNC
  • Elaborazione basata su cluster
  • Debugging
  • Strumenti di sviluppo
  • Architettura Intel® Many Integrated Core
  • Ottimizzazione
  • Elaborazione parallela
  • Porting
  • BKMs on the use of the SIMD directive

    We had an ask from one of the various “Birds of a Feather” meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences. The customer wanted to know BKMs (Best Known Methods) on the proper usage of the new OpenMP* 4.0 / Intel® Cilk™ Plus SIMD directive. I volunteered to create such a list. Investigating the topic more thoroughly, I discovered that there is already a vast amount of resources on vectorization and the use of the SIMD directive.

    Resource Guide for Intel® Xeon Phi™ Coprocessor Administrators

    This article makes recommendations for how an administrator can get up to speed quickly on the Intel® Many Integrated Core (Intel® MIC) Architecture. This article is 1 of 3: For the Administrator, for the Developer, and for the Investigator. Someone who will administer and support a set of machines (individual/cluster) containing coprocessors. The assumption is that the following topics are of most interest to him. Administrative tools and configurations for the Intel Manycore Platform Software Stack (Intel MPSS) Technical support services Library support Language support Network infrastructure Installation documentation Cluster administration and FAQ Scripting support
  • Sviluppatori
  • Professori
  • Studenti
  • Linux*
  • Microsoft Windows* (XP, Vista, 7)
  • Microsoft Windows* 8.x
  • Server
  • C/C++
  • Fortran
  • Avanzato
  • server
  • Parallel Programming
  • Taylor Kidd
  • Intel Xeon Phi Coprocessor
  • MIC
  • Knights Corner
  • manycore
  • Many Core
  • KNC
  • Elaborazione basata su cluster
  • Debugging
  • Strumenti di sviluppo
  • Architettura Intel® Many Integrated Core
  • Elaborazione parallela
  • Porting
  • Resource Guide for Intel® Xeon Phi™ Coprocessor Developers

    This article makes recommendations for how a developer can get up to speed quickly on the Intel® Many Integrated Core (Intel® MIC) Architecture. This is one of three articles: For the Administrator, for the Developer, and for the Investigator. Who is a Developer? Someone who will be programming on an Intel Many Integrated Core (Intel MIC) architecture. The assumption is that they are most interested in: Brief Introduction to the Intel MIC development environment Programming models Hardware architecture Software stack Coprocessor specific drivers and tools – Intel Manycore Platform Software Stack (Intel MPSS) Compilers Libraries Tools Examples and tutorials SW Developer’s Guide Programmer’s Guide Optimization Guide Getting help and other support
  • Sviluppatori
  • Professori
  • Studenti
  • Linux*
  • Server
  • C/C++
  • Fortran
  • Avanzato
  • server
  • Parallel Programming
  • Taylor Kidd
  • Intel Xeon Phi Coprocessor
  • MIC
  • Knights Corner
  • manycore
  • Many Core
  • KNC
  • Elaborazione basata su cluster
  • Architettura Intel® Many Integrated Core
  • Elaborazione parallela
  • Efficienza energetica
  • Iscriversi a MIC