Fault simulation for sequential circuits numbers among the highly compute-intensive tasks in the integrated circuit design process. In this paper we propose a new parallel fault simulation algorithm for multi-core workstations with common memory. We use dynamic fault grouping for each input test vector. Also each formed group is simulated in separate thread. Also we study the scalability of proposed algorithm. We report results for the ISCAS-89 benchmark circuits obtained on Intel’s MTL with 12 computational cores.