Intel® Streaming SIMD Extensions

Instruction set extensions programming reference, revision 18

In early February, an updated instruction set extensions programming reference, revision 18, has been posted here.

It includes information about:

  • Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions
  • Intel® Secure Hash Algorithm (Intel® SHA) extensions
  • Intel® Memory Protection Extensions (Intel® MPX)

For more information about the technologies: http://www.intel.com/software/isa

Updated Intel® Software Development Emulator

Hello, we just released version 6.20 of the Intel® Software Development Emulator. It is available here:http://www.intel.com/software/sde

It includes:

  • Added support for XSAVEC and CLFLUSHOPT.
  • Disabled TSX CPUID bits when TSX emulation is not requested.
  • Improved disassembly for MPX instructions.
  • Added an option for running chip-check only on the main executable.
  • Added support for -quark (Pentium ISA).
  • Added application debugging for Mac OSX with the lldb debugger.

Using the Intel® IPP Library in an Embedded System – Linkage Model Size Differences

If you are familiar with the Intel® Integrated Performance Primitives (Intel® IPP) library you know that it is widely used to build applications built for the Microsoft* Windows* and Linux* operating systems – today's most prevalent "standard" desktop and server operating system (OS) platforms. What you may not know is that the Intel IPP library can also be used with applications built for some embedded and real-time operating systems (RTOS).

  • Intel® Integrated Performance Primitives
  • Intel® Streaming SIMD Extensions
  • dynamic link
  • SSE
  • static link
  • embedded
  • Different ways to turn an AoS into an SoA

    Hi,

    I'm trying to implement a permutation that turns an AoS (where the structure has 4 float) into a SoA, using SSE, AVX, AVX2 and KNC, and without using gather operations, to find out if it worth it.

    For example, using KNC, I would like to use 4 zmm registers:

    {A0, A1, ... A15}

    {B0, B1, ... B15}

    {C0, C1, ... C15}

    {D0, D1, ... D15}

    to end up having something like:

    {A0, A4, A8, A12, B0, B4, B8, B12, C0, C4, C8, C12, D0, D4, D8, D12}

    {A1, A5, A9, ...}

    {A2, A6, A10, ...}

    {A3, A7, A11, ...}

    Trusted Tools in the New Android* World: Optimization Techniques - from Intel® SSE Intrinsics to Intel® Cilk™ Plus

    Author: Zvi Danovich, Senior SW Application Engineer, Intel

    Introduction

    Most Android applications, even those based only on scripting and managed languages (Java*, HTML5,…), eventually use middleware features that would benefit from optimization.

    This paper will discuss optimization needs and approaches on Android and walk through a case study of how to optimize a multimedia and augmented reality application.

  • Sviluppatori
  • Android*
  • Android*
  • Intel® Cilk™ Plus
  • Intel® SSSE3; RGB Transformation; Parallelization
  • Intel® Streaming SIMD Extensions
  • Grafica
  • Ottimizzazione
  • Elaborazione parallela
  • Parallel Computation of Sparse Rulers

    This article explains the sparse ruler problem, two parallel codes for computing sparse rulers, and some new results that reveal a surprising "gap" behavior for solutions to the sparse ruler problem. The code and results are included in the attached zip file.

    Background

    A complete sparse ruler is a ruler with M marks than can measure any integer distance between 0 and L units. For example, the following ruler has 6 marks (including the ends) and can measure integer distance from 0 to 13:

  • Sviluppatori
  • Professori
  • Studenti
  • C/C++
  • Intermedio
  • Intel® Cilk™ Plus
  • Cilk Plus
  • Intel® Streaming SIMD Extensions
  • Elaborazione parallela
  • Instruction set extensions programming reference, revision 17,

    An updated instruction set extensions programming reference, revision 17, has been posted here. 

    It includes information about:

    • Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions
    • Intel® Secure Hash Algorithm (Intel® SHA) extensions 
    • Intel® Memory Protection Extensions (Intel® MPX) 

    For more information about the technologies: http://www.intel.com/software/isa

     

    Créer des applications NDK Android* avec Intel® Integrated Performance Primitives (Intel® IPP)


    Intel® Integrated Performance Primitives (Intel® IPP) fournit des composants hautement optimisés pour le traitement des images, le traitement des signaux, les mathématiques vectorielles et les calculs de petites matrices. Plusieurs domaines Intel IPP contiennent les fonctions réglées manuellement pour processeur Intel® Atom™ en tirant parti des instructions Intel® Streaming SIMD Extensions (Intel® SSE). Les bibliothèques Intel IPP statiques sans threads Linux* prennent maintenant en charge le SE Android* et peuvent être utilisées avec les applications Android.

  • Sviluppatori
  • Android*
  • Android*
  • Java*
  • Intel® Integrated Performance Primitives
  • Intel® Streaming SIMD Extensions
  • SSE4.2
  • ndk
  • Processori Intel® Atom™
  • Iscriversi a Intel® Streaming SIMD Extensions