Watercooler / Catchall

moderation queue

Is there a way to check our posts which are pending moderation?  I suppose it's understandable that moderation could take 3 days or longer, but it would be useful to be able to confirm whether posts are still pending or entirely lost.


windows 8

Hi all, I am not sure if this is the right place to post this question but all other forums sounded like they would've been the wrong place, so please forgive me if this is the wrong place too. Tonight I picked up a dell venue 7 which comes with android, with the hopes of installing my copy of windows 8.1 on it. I opted for the 7 over the 8 pro because believe it or not there is a major difference in size and i'm seeking mobilty, something I can easily put in my back pocket.

"The worst" Windows NT description of an event I've ever read

I think this is "the worst" Windows NT description of an event I've ever read:
Bucket -295570786, bucket table 5, EventType mptelemetry, P1 0x8007066f, P2 patchapplication, P3 am bdd, P4 11.1.4501.0, P5 mpsigstub.exe, P6 4.4.304.0, P7 microsoft security essentials, P8 NIL, P9 NIL, P10 NIL.

Developer's manual: 0x66 0xF2 instruction prefixes

I'm reading "Intel® 64 and IA-32 Architectures Software Developer’s Manual" but I have a doubt about some opcode sequences.

Suppose to have this opcode sequence: "66 F2 0F 38 29 1E". According to Intel manual the opcodes sequence should be valid and the correct disasmed instruction is "repne pcmpeqq xmm3, xmmword ptr [esi]". I have seen some disassemblers mark the sequence as an invalid instruction; is there a specific 3 byte opcode table (256 entries defined by the 3° opcode) where "66F20F38" initial sequence is always invalid except for the 0xF0 and 0xF1 cases?

DVFS on Intel SandyBridge

Hi All,

I wanted to experiment with DVFS on Intel SandyBridge and through the Intel Manual 3B, I see that the DVFS is achieved on SandyBridge using Enhanced Intel SpeedStep.

It says that IA32_PERF_CTL could be set to achieve DVFS. However the Manual does not explain how to set the lower 16 bits in IA32_PERF_CTL to achieve this. I went across searching on different forums to ascertain how to set this to no avail. However, what I could learn is that the 16 bits are divided into two 8-bit blocks that specify the Multiplier and VID. 

How to configure SNMP TRAPS

Hi All,

        I need your help to configure the SNMP traps configure.I am not sure i am posting the right place or not.

I am using intel S2600GZ server board and installed SNMP subagent version snmpsa-5.0.0-14.x86_64.rpm and i am running on the Suse linuux

SUSE Linux Enterprise Server 11 (x86_64)


I am able to install snmpsa rpm successfully.

I would like to received the traps in another windows machine.For that I added below entried in the snmpd.conf file

rwcommunity  public

DVFS for atom D2000 processor

This is my first exposure to DVFS and I would like to be clarified on a few points

The data sheet for the processor says that it supports lots of P-states. 

It also says that

Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency:

My questions are

Is it possible to independently set the voltage/frequency and if so how and to which register do we write to?

What are values for various frequencies?





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