25-mar-2014
1:34 PM PDT
Resource Guide for Intel® Xeon Phi™ Coprocessor Administrators
By Taylor Kidd (Intel)Posted 03/25/20140
This article makes recommendations for how an administrator can get up to speed quickly on the Intel® Many Integrated Core (Intel® MIC) Architecture. This article is 1 of 3: For the Administrator, for the Developer, and for the Investigator. Someone who will administer and support a set of machi...
24-mar-2014
3:47 PM PDT
Intel® Trace Analyzer and Collector 9.0 Beta Update 1 Readme
By Gergana Slavova (Intel)Posted 03/24/20140
The Intel® Trace Analyzer and Collector is a low-overhead scalable event-tracing library with graphical analysis that reduces the time it takes an application developer to enable maximum performance of cluster applications. This Beta package is for users who develop on and build for Intel® 64 arc...
24-mar-2014
3:29 PM PDT
Intel® MPI Library 5.0 Beta Update 1 Readme
By Gergana Slavova (Intel)Posted 03/24/20140
The Intel® MPI Library is a high-performance interconnect-independent multi-fabric library implementation of the industry-standard Message Passing Interface, v3.0 (MPI-3.0) specification. This Beta package is for MPI users who develop on and build for Intel® 64 architectures on Linux* and Windows...
22-mar-2014
11:36 PM PDT
Intel® Math Kernel Library Parallel Direct Sparse Solver for Clusters
By Alexander Kalinkin (Intel)Posted 03/22/20140
The Intel® Math Kernel Library Parallel Direct Sparse Solver for Clusters (CPARDISO) is a powerful tool set for solving system of linear equations with sparse matrix of millions rows/columns size. CPARDISO provides an advanced implementation of the modern algorithms and could be considerate as ...
18-mar-2014
5:51 PM PDT
Conservative Morphological Anti-Aliasing (CMAA) - March 2014 Update
By Robert Svilpa (Intel)Posted 03/18/20140
This article was taken from a blog posting on IDZ by Leigh Davies at Intel Corp, highlighting work and results completed by Leigh and his colleague Filip Strugar in the new AA technique being referred to as Conservative Morphological Anti-Aliasing. Below is the content of the blog along...
18-mar-2014
12:21 AM PDT
Controlling memory consumption with Intel® Threading Building Blocks (Intel® TBB) scalable allocator
By Kirill Rogozhin (Intel)Posted 03/18/20142
The Intel® Threading Building Blocks (Intel® TBB) library provides an alternative way to allocate dynamic memory - Intel TBB scalable allocator (tbbmalloc). Its purpose is to provide better performance and scalability for memory allocation/deallocation operations in multithreaded applications, co...
10-mar-2014
1:50 PM PDT
Contest Winners Combine Augmented Reality with an Encyclopedia with ARPedia*
By Jerry Baugh (Intel)Posted 03/10/20140
By Garret Romaine The interfaces of tomorrow are already in labs and on test screens somewhere, waiting to turn into fully developed samples and demos. In fact, look no further than the winner of the Creative User Experience category in the Intel® Perceptual Computing Phase 2 Challenge, announce...
10-mar-2014
9:02 AM PDT
Head of the Order* Casts a Spell on Perceptual Computing
By Jerry Baugh (Intel)Posted 03/10/20140
By Edward J. Correia When Intel put a call out for apps that would transform the way we interface with traditional PCs, Jacob and Melissa Pennock, founders of Unicorn Forest Games, entered their spell-casting game, Head of the Order*, into the Intel® Perceptual Computing Challenge. They took hom...
10-mar-2014
8:48 AM PDT
Intel® Advisor 2015 Beta Tutorials: Windows* OS
By Nancee Moster (Intel)Posted 03/10/20140
Discover how to find where to add parallelism to a serial application using the Intel® Advisor and the nqueens_Advisor C++ sample application. This short tutorial demonstrates an end-to-end workflow you can ultimately apply to your own applications: Survey the target to locate the loops and fu...
07-mar-2014
4:25 PM PST
Diagnostic 15002: loop was vectorized (Fortran)
By Martyn Corden (Intel)Posted 03/07/20140
  Cause: For the Intel® Compiler, vectorization is the unrolling of a loop combined with the generation of packed SIMD instructions. Because the packed instructions operate on more than one data element at a time, the loop can execute more efficiently. The above message indicates that the loop ...

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