In Intel IPP v6.0, there is a new function named ippGetCpuFeatures() (*) that can be used to detect your processor features. It is declared in ippcore.h. This function retrieves CPU features like those returned by the Linux function CPUID.1 and stores them consecutively in the mask pFeaturesMask. The following table lists features stored in the mask. Mask values are defined in the ippdefs.h file.
Note as of version 6.1 the IPP library supports the new Intel® Advanced Vector Extensions ( Intel® AVX) instruction.
Please refer to Intel IPP developer reference guide https://software.intel.com/en-us/node/502018 for latest processor.
Note that the legacy IPP function ippGetCpuType() (**) mixed CPU types and SIMD instruction types. Starting with version 6.0 of the library we strongly recommend using this new function ippGetCpuFeatures() to detect the CPU feature.
Additionally, please download the Intel IPP samples (***) which contain an application that can be used to detect a range of CPU info. This free sample, with source code, is located in the ipp-samples\advanced-usage\cpuinfo directory of the IPP samples.
Processor Architecture Table
The following table was copied from an Intel Compiler Pro options article describing some compiler architecture options. It contains a fairly complete list of which Intel processors support which SIMD instructions. For the latest table please refer to the original article; it gets updated on a regular basis. Please note that the behavior of the Intel Compiler SIMD dispatcher described in that article does not apply to the Intel IPP library. The Intel IPP library dispatching mechanism behaves differently than that found in the Intel Compiler products, and may behave differently than other Intel library products.
Intel® Core™ i7 Processors
Intel® Xeon® 55XX series
Intel® Xeon® 74XX series
Quad-Core Intel® Xeon 54XX, 33XX series
Dual-Core Intel® Xeon 52XX, 31XX series
Intel® Core™ 2 Extreme 9XXX series
Intel® Core™ 2 Quad 9XXX series
Intel® Core™ 2 Duo 8XXX series
Intel® Core™ 2 Duo E7200
Quad-Core Intel® Xeon® 73XX, 53XX, 32XX series
Dual-Core Intel® Xeon® 72XX, 53XX, 51XX, 30XX series
In tel® Core™ 2 Extreme 7XXX, 6XXX series
Intel® Core™ 2 Quad 6XXX series
Intel® Core™ 2 Duo 7XXX (except E7200), 6XXX, 5XXX, 4XXX series
Intel® Core™ 2 Solo 2XXX series
Intel® Pentium® dual-core processor E2XXX, T23XX series
Dual-Core Intel® Xeon® 70XX, 71XX, 50XX Series
Dual-Core Intel® Xeon® processor (ULV and LV) 1.66, 2.0, 2.16
Dual-Core Intel® Xeon® 2.8
Intel® Xeon® processors with SSE3 instruction set support
Intel® Core™ Duo
Intel® Core™ Solo
Intel® Pentium® dual-core processor T21XX, T20XX series
Intel® Pentium® processor Extreme Edition
Intel® Pentium® D
Intel® Pentium® 4 processors with SSE3 instruction set support
Intel® Xeon® processors
Intel® Pentium® 4 processors
Intel® Pentium® M
Intel® Pentium® III Processor
Intel® Pentium® II Processor
Intel® Pentium® Processor
* Intel(R) IPP versions 6.0, 6.1, 7.0 and 7.1 are no longer supported. The current version of Intel(R) IPP is 8.2 which is bundled with Intel Composer XE 2015.
** since the Intel® IPP 8.2, the following domains are beginning the deprecation process, and we want to learn your feedback
*** these IPP Samples package is now legacy. Please see the article to get more detailed info about this process "https://software.intel.com/en-us/forums/topic/401253"
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804