Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:
- Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
- Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
- Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
- Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
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Adesivo:
Intel® Software Development Emulator release 7.30 por Mark Charney (Intel) |
seg, 21/09/2015 - 05:23 |
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Adesivo:
Resources about Intel® Transactional Synchronization Extensions (Intel TSX) por Roman Dementiev... |
sex, 07/06/2013 - 06:46 |
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Links to instruction documentation por Thomas Willhalm... |
sex, 31/12/2010 - 07:07 |
Tópico normal
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Enabling Mon feature using IA32_MISC_ENABLES por K., Sina |
seg, 09/04/2018 - 23:24 |
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Possible errors in instruction semantics por Dasgupta, Sandeep |
qua, 04/04/2018 - 17:48 |
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Immediate operands for SSE instructions? por Luchezar B. |
qui, 22/03/2018 - 08:48 |
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Support for saturation and addition instruction in AVX-512 por Udupi, Nagacharan |
seg, 19/03/2018 - 12:39 |
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Vector processing needs better NAN propagation por Agner |
seg, 19/03/2018 - 00:41 |
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Performance delays - programming with QNan and Denormals por zalia64 |
ter, 13/03/2018 - 08:12 |
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How to get the FLOP number of an application? por zhang t. |
sex, 02/03/2018 - 17:51 |
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Histogram examples using AVX-512 CD in Dec 2017 Optimization Ref Manual are wrong? por Nelson, Trent |
qui, 01/03/2018 - 06:37 |
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How to Reduce CAL (Function Call Interrupts ) on x86_64 architectures in /proc/interrupts por Kumar, Satish |
ter, 20/02/2018 - 00:00 |
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Parallel dependence in bitmap scaling code por CommanderLake |
sab, 03/02/2018 - 18:55 |
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If the frequency is set to the P_STATE 1, why AVX-512 is not running to its base frequency? por Jordi V. |
ter, 23/01/2018 - 12:32 |
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AVX-512 VBMI2: why no vector version of _pext_u32()? por Mikkelsen, Morten |
qui, 11/01/2018 - 16:24 |
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Update the SDE MSVS debugger install kit to support VS2017? por Ens, John |
sex, 22/12/2017 - 07:40 |
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AVX512-VBMI2: VPSHLDV masks its shift count preventing use as a blend por Peter Cordes |
sab, 09/12/2017 - 12:23 |
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SSE and AVX behavior with aligned/unaligned instructions por Mark D. |
qui, 07/12/2017 - 14:17 |
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Is the guide of Gather/Scatter of AVX512 wrong? por He, Jiayuan |
sex, 01/12/2017 - 02:07 |
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AVX512 missing intrinsics por Cloyz |
sab, 25/11/2017 - 15:38 |
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Older versions of Intel Intrinsics Guide: data-X.X.X.xml file por Alen Stojanov |
sex, 24/11/2017 - 04:36 |
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Array Registers por Daniel F. |
sab, 18/11/2017 - 02:44 |
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Convert bytes to nibbles por CommanderLake |
ter, 07/11/2017 - 07:56 |
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AVX vs. SSE: expect to see a larger speedup por Anuj G. (Intel) |
dom, 05/11/2017 - 13:16 |
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AVX512 auto-vectorization on i9-7900X por Marko S. |
qui, 02/11/2017 - 11:50 |
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