In the SDM, the MSR IA32_PRED_CMD (0x49) can be read if CPUID(EAX=07H, ECX=0):EDX equals 1
For example, processor Xeon W3690 of architecture Westmere/Gulftown, microcode version 31, is capable of IBRS & IBPB, according to the EDX register of CPUID leave 7. However, reading the MSR 0x49 will immediately crash processor [whereas MSR IA32_SPEC_CTRL (0x48) works as specified]
FYI, same issue has been encountered with a i7-6700 Skylake processor
Question: what are the discriminant bits to safely read the MSR IA32_PRED_CMD ?