Understanding hardware performance counter event for STLB flush

Understanding hardware performance counter event for STLB flush

Hello,

     I was trying to count number of fluhses to TLB using performaqnce counters. One of the event that looked interesting to me is the "TLB_FLUSH.STLB_ANY" with event number BDH and mask 20H. The System Programing guide 3B (http://download.intel.com/products/processor/manual/253669.pdf)  mentions that this measures  "Count number of STLB flush attempts".  Does this mean that this counts the number of TLB flusehes for the second level TLB? Does any body have better understanding of what this event really counts.

I am more confused by the fact that when I measure another related counter TLB_FLUSH.DTLB_THREAD (same event number but mask is 01H and supossedly counts DTLB flush attempts of the thread-specific entries), it shows a much smaller value than the measured value of TLB_FLUSH.STLB_ANY. I am not understanding under what circumstances the L1 DTLB will not be flushed but STLB will be flushed. I should be missing something. Can somebody help me out here?  Any body has an idea how these are related too writes to CR3  and/or CR4 registers?

Thanks

Arka

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What do STLB and DTLB stand for?

>>> I was trying to count number of fluhses to TLB using performaqnce counters.>>>

How do you manage to read the values of the MSR registers?Do you use DbgPrint function in your driver?

@illya

DTLB = Data Translation Lookaside Buffer (generally used to refer Level 1 TLB for Data)
STLB = Second level/Shared TLB (L2 TLB).

I used oprofile to read the performance counter values.

Citação:

arkaprava.basu escreveu:

@illya

DTLB = Data Translation Lookaside Buffer (generally used to refer Level 1 TLB for Data)
STLB = Second level/Shared TLB (L2 TLB).

I used oprofile to read the performance counter values.


Hi!
Thanks for answer.
What is oprofile?
Do you use Linux or Windows?

@arkaprava
Have you ever tried to write your own driver for accessing MSR register?

@ilya

there are user-space frameworks to access hardware performance counters from user space already in place, so 99% of users do not need to directly program low-level registers (MSR) to read processor performance data. Consider Linux perf, Intel Performance Counter Monitor or PAPI for example.

Intel VTune Amplifier XE, Linux perf and oprofile are profilers using processor hardware performance counters (but there are certainly more than that).

Best regards,

Roman

>>>@ilya

there are user-space frameworks to access hardware performance counters from user space already in place, so 99% of users do not need to directly program low-level registers (MSR) to read processor performance data. Consider Linux perf, Intel Performance Counter Monitor or PAPI for example.>>>

Thanks Roman.

Citação:

iliyapolak escreveu:

>>>@ilya

there are user-space frameworks to access hardware performance counters from user space already in place, so 99% of users do not need to directly program low-level registers (MSR) to read processor performance data. Consider Linux perf, Intel Performance Counter Monitor or PAPI for example.>>>

Thanks Roman.

Hi Roman!

How I can integrate Intel performance monitor API into my code?

Thanks in advance.

Hi Ilya,

you can look at this blog for an example of integration.

Thanks,

Roman

@Roman

Thanks for your help.I think that I will try to "mess" with MSR registers by writing my own drivers.

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