Does the cache prefetcher will abort the rtm transaction?

Does the cache prefetcher will abort the rtm transaction?

Does a cache line prefetched in the RTM region will evict some cache line in the read set or write set and cause the transaction abort ?

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Even if Intel Software Development Manual ( SDM ) does not describe it explicitly I think Yes and it is very possible in some cases.

For eample, there is a statement on a page 329 in a latest version of Intel SDM:

'...the following instructions may always cause transactional aborts... ...memory instructions with a non-temporal hint...'

and it means that _mm_prefetch( pAddress, { _MM_HINT_T0 | _MM_HINT_T1 | _MM_HINT_T2 } ) could cause transactional abort and

_mm_prefetch( pAddress, _MM_HINT_NTA ) could not.

Thanks for your reply. Does the some prefetch policy like adjacent cache lline prefetch will also evict a cache line already in the write set?

And do you have any idea about how to disable the hardware cache prefetcher? I try to disable haswell cache prefetcher, but there is no options in the BIOS. I also can't find  any msr bit can be used to disable the cache prefetcher in the SDM for the haswell. 

Prior to the protected region, can you explicitly touch the questionalble locations? (and/oror prefetch)

Jim Dempsey

>>...And do you have any idea about how to disable the hardware cache prefetcher? ..

I don't know if some computers allow to disable it partially or completely through the BIOS settings. For example, my Dell Precision M4700 doesn't have such feature. Please also take a look at some generic comments I found ( you're trying that way... ):

It is possible to completely or partially disable hardware prefetching for the entire processor.
On Intel processors an Model Specific Register (MSR) is used for this ( IA32 MISC ENABLE,
bit 9 on many processors; bit 19 disables only the adjacent cache line prefetch). This, in
most cases, has to happen in the kernel since it is a privileged operation. If profiling shows
that an important application running on a system suffers from bandwidth exhaustion and premature
cache evictions due to hardware prefetches, using this MSR is a possibility.


If the passed pointer references valid memory, the prefetch unit will be instructed to load the
data into cache and, if necessary, evict other data.

Unfortunately the MSRs used to disable various prefetchers are different for each Intel processor family, and documentation is not available in public documents.   In many cases, some or all of the hardware prefetchers can be disabled through the BIOS, but this is not a required feature.

John D. McCalpin, PhD "Dr. Bandwidth"

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