The proposed solution is one of the multiple ways to optimize the memory access and is used for demonstration purposes only.
multiply2function swaps the indices of the innermost two loops, in a method called loop interchange. Note in the innermost loops that three of the array references use
jas the second index and the fourth reference does not use
jat all. In C that last index addresses locations adjacent in memory sequence, taking advantage of cache locality to use adjacent data all in one pass, and that optimizes the memory access in the code by minimizing cache line thrash. Moreover, arranging successive computations in array order this way makes them more likely to be recognized by the compiler for vectorization.
When you build the code with the Intel® C++ Compiler, it vectorizes the computation, which means that it uses SIMD (Single Instruction Multiple Data) style instructions that can work with several data elements simultaneously. If only one source file is used, the Intel compiler enables vectorization automatically. The current sample uses several source files, which is why the
#pragma ivdepto instruct the compiler to ignore assumed vector dependencies. This information lets the compiler employ the Supplemental Streaming SIMD Extensions (SSSE).
Re-run the application via
You see that the Execution time has reduced significantly and you got about 27 seconds of optimization.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804