PCI-Express Interface Specifications

The compute module provides one PCI-Express 2.0 lane, and all required side-band signals, through the J7 connector.

Within the module, the primary PCI-Express signals are multiplexed with the USB3.0 interface; a BIOS setting determines if these lines functions as PCI-Express or USB3, a then BIOS must be re-flashed to change back and forth.

Note: PCI-Express and USB3 cannot be used at the same time.

M2 Connector Details

Signal Name Module Connector / Pin Number Direction Usage
PCIE_RX_DP J7.95 Input PCI-Express Receive Data (positive)
PCIE_RX_DN J7.97 Input PCI-Express Receive Data (negative)
PCIE_TX_DP J7.87 Output PCI-Express Transmit Data (positive)
PCIE_TX_DN J7.89 Output PCI-Express Transmit Data (negative)
PCIE_CLK_DP J7.86 Output PCI-Express Clock (positive)
PCIE_CLK_DN J7.88 Output PCI-Express Clock (negative)
PCIE_CLKREQ J7.50 Input PCI-Express Clock Request
PCIE_WAKE J7.72 Output PCI-Express Wake
PCIE_PERST J7.70 Output PCI-Express Reset


  1. The PCI-Express Transmit signals (PCIE_TX_DP / PCIE_TX_DN) have series AC capacitors designed into the signals located on the Intel® Joule™ Module.  It is up to the board designer to ensure that series AC capacitors are correctly placed on the PCI-Express Receive signals (PCIE_RX_DP / PCIE_RX_DN).
  2. The PCI-Express sideband signals (CLKREQ, WAKE, & PERST) need to be level shifted from 1.8V to 3.3V for proper operation.

The compute module has an integrated PCIe* interface with the following features:

PCIe* Interface Category Description
PCIe* Interface PCIe* Gen 2
PCIe* number of lanes 1 lane multiplexed with USB 3.0
PCIe* maximum supported devices Up to 2 root ports/external devices
PCIe* signal transfer rate PCIe* Gen 2 5.0 GT/sec
PCIe* clock frequency 100 MHz (SSC/NSSC Type)
Supports 4 reference clocks (REF CLK)

PCIe Compliance

PCIe is compliant with the PCI Express* Base Specification Revision 2.0.


Para obter informações mais completas sobre otimizações do compilador, consulte nosso aviso de otimização.