Intel® Developer Zone:
Monitoramento de plataforma

Bem-vindo(a) à Comunidade de monitoramento de plataforma!

Aqui você encontrará informações que tratam do monitoramento de desempenho e do ajuste de software, bem como tópicos sobre o monitoramento de plataformas. O monitoramento de desempenho cobre uma variedade de tópicos, dentre os quais se incluem uma introdução às metodologias de monitoramento e ajuste de software, assim como técnicas de otimização de software e métodos mais conhecidos para usuários novatos e avançados.

Para os desenvolvedores, há os manuais de consulta de programação com as informações mais recentes que descrevem a interface de hardware da PMU (Performance Monitoring Unit - unidade de monitoramento de desempenho) dos microprocessadores Intel e os recursos de monitoramento dos componentes Uncore, além de fontes de informações sobre os eventos de desempenho que podem ser monitorados.

O monitoramento de plataforma inclui tópicos sobre o monitoramento de máquinas, como o monitoramento dos componentes Core da CPU, de processadores gráficos, de coprocessadores de outros sistemas e recursos de medição e de qualidade de serviços.

Platform Monitoring Frequently Asked Questions
By Posted 09/15/20100
Introduction This is an organic document, meaning, that it will expand as need and request dictate. The purpose is to help establish a repository of common and perhaps not-so-common questions that arise while optimizing systems using Platform Monitoring processes. Platform Monitoring Overview 1....


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Memory Bandwidth on 2 socket Xeon E5-2670 without uncore counters
By Darko Z.3
Hi, I need to measure memory bandwidth on a data-center where each node is a 2 socket Xeon E5-2670. I know it can be measured with Uncore performance counters (iMC performance monitoring CAS_COUNT) as described in Intel Xeon E5-2600 Product Family Uncore Performance Monitoring Guide, but when I look in /sys/bus/event_source/devices/ there is no uncore counters... (I guess this is because it runs old Linux kernel 3.0, but unfortunately I cannot change this, nor I can be root). I have also tried using perf with raw events (umask and event code i found in previous document -- Intel Xeon E5-2600 Product Family Uncore Performance Monitoring Guide), but I am not sure whether these readings are correct -- moreover I didn't find umask and event code for each memory channel, but just one. 1. Can anybody comment on this and show me hoe to get umask and event code for all channels? 2. Is there any formula for the measurement of memory bandwidth that uses only Core performance counters on Xeon ...
Timely interaction of performance counters
By Olaf Krzikalla8
Hi @all, ist there an in-depth explanation of the timely interaction of performance counters (esp. cache miss counters) with the rest of the code? Maybe a specific section in App.B of the Optimization Reference Manual I have missed so far? An example: (pmc configured for counting L1D cache misses) rdpmc (store eax) mov xmm0, [esi] // read from [esi] mov xmm1, [edi] // read from [edi] rdpmc Now assume, that esi and edi both point to the same location, which initially is not in L1. Then, which difference of the L1 pmc will be observable?  And why? IMHO there are a lot of things (pipelining, out-of-order-execution, stalling), which can influence the result. Is this documented? Thanks for your help Olaf  
Monitoring Intel platforms with WBEM/CIM, SNMP
By Thor T.0
Hi, I am looking for documentation that would help me understand what platform monitoring abilities exist, if any, for Intel Server Systems. I've read up on Intel AMT, SNMP sub agent and the likes but fail to understand how the system information and what information is made available. Other system vendors have agent based solutions such as HP Insight Manager Agent, Dell OpenManage Server Administrator and IBM Director that provide monitoring access to the system by use of WBEM and CIM providers. One would then tap into these systems using SNMP or WMI to gather system information such as CPU temperature, FAN speeds, Power Supply status, disk and controller status etc. I am looking for a similar offering from Intel. Does this exist and if so, what is it called and where can it be downloaded? Thanks for reading.
Is there an interaction between P-states and C1 state?
By John D. McCalpin0
I have found lots of references that say that there is no interaction between P-states and C-states, but I am curious about one specific case that might have an interaction. In the C1 state, the core clocks are stopped, but the private caches remain active.  If a processor is in a low-frequency P-state (e.g., 1.2 GHz on a 2.7 GHz Sandy Bridge core) when it enters C1 (via MONITOR/MWAIT), do the caches continue to operate at the low frequency?  Or do the caches not pay attention to the core multiplier ratios? If the caches do run slower at the higher-numbered P-states, then I have questions about how the L2 to System Agent manages the (presumably) asynchronous clock boundary with the Rings, since the Rings appear to run at the speed of the fastest core -- but that is probably too much detail for a public forum.   Actually, I have no experimental evidence that the cores in my Xeon E5-2680 (Sandy Bridge EP) are capable of running at different frequencies at the same time.   I can static...
All-core Turbo on Xeon E5-v2 Processors
By John S.5
I was looking for some quick statistics on turbo mode on the new E5-v2 processors.  The turbo frequency listed on the ARK site only applies when one core is being turbo'd, right?  I would like to know what frequency all cores can safely turbo to at all times for the E5-2667v2 and E5-2643v2.  Does anyone have these numbers?
IPSec Offload no controlador 82576GB
By Rodrigo Leal1
Como Usar o IPSec Offload no Sistema Operacional Linux (Ubuntu)?
Custom software.
By Max V.0
Custom software design, coding, development, programming, testing services Software development outsourcing  
Measuring executed floating-point operations on Haswell
By arbor3
Hi, I'm trying to measure the amount of floating-point operations executed on a processor with Haswell microarchitecture using performance counters under Linux. So far, I managed to measure the amount of (single precision) float multiplications using the UOPS_ISSUED.SINGLE_MUL performance event. However, this event only counts the amount of float multiplications while ignoring float additions, comparisons as well as any operations involving doubles. I also tried accessing the FP_COMP_OPS_EXE.* events (such as FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE) from the SandyBridge and IvyBridge microarchitectures via their raw event codes using the perf tool under Linux. The resulting counter values were always 0. Is there any way to measure the amount of float additions, comparisons, divisions as well as operations on doubles on the Haswell microarchitecture? Thanks in advance


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Destaques mostrados pelo gerente da comunidade

Em 05 de janeiro de 2011, a Intel lançou a segunda geração da família de processadores Intel® Core™ (que tinha o codinome de Sandy Bridge) para laptops e PCs. Os novos processadores têm uma nova arquitetura revolucionária, que combina o "cérebro" computacional (ou microprocessador) com um mecanismo gráfico no mesmo chip pela primeira vez. Os novos recursos incluem o Intel® Insider™, o Intel® Quick Sync Video e uma nova e premiada versão do Intel® Wireless Display (WiDi), que agora tem alta definição de 1080p e recursos de proteção de conteúdo para os usuários que quiserem passar conteúdo de alta definição da tela do laptop para a TV.

Fique ligado. Volte sempre. Nós vamos publicar os manuais de programação da PMU e ferramentas atualizadas para dar a você as informações mais recentes sobre as inovações da microarquitetura Intel.