Intel® Developer Zone:
Segurança e criptografia

Novas instruções AES

Gerador digital de números aleatórios

Extensões da Instruction Set Architecture da Intel

Intel® Xeon™ E5-2600 v3 Product Family
Por BELINDA L. (Intel)Publicado em 09/08/20140
Based on Intel® Core™ microarchitecture (formerly codenamed Haswell) and manufactured on 22-nanometer process technology, these processors provide significant performance over the previous-generation Intel® Xeon™ processor E5-2600 v2 product family. This is the first Intel® Xeon® processor fami...
How to use the rdrand engine in OpenSSL for random number generation
Por John Mechalas (Intel)Publicado em 07/30/20140
The OpenSSL* ENGINE API includes an engine specifically for Intel® Data Protection Technology with Secure Key. When this engine is enabled, the RAND_bytes() function will exclusively use the RDRAND instruction for generating random numbers and will not need to rely on the OS's entropy pool for re...
Meshcentral - Introduction & Overview
Por ylian-saint-hilaire (Intel)Publicado em 07/03/20140
  Site Links Main site: meshcentral.com Information site: info.meshcentral.com Developer blog: intel.com/software/ylian Overview Meshcentral is an open source project under Apache 2.0 license that allows administrators to remotely manage computers over the Internet using a single web port...
Intel® Digital Random Number Generator (DRNG) Software Implementation Guide
Por John Mechalas (Intel)Publicado em 05/14/201423
Revision 2.0 May 15, 2014 Downloads Download Intel® Digital Random Number Generator (DRNG) Software Implementation Guide [PDF 975KB]Download Intel® Digital Random Number Generator software code examples Related Software Download Rdrand manual and library (Linux* and OS X* version)Download Rd...
Assine o Artigos do Espaço do desenvolvedor Intel
Nenhum conteúdo foi encontrado
Assine o Blogs do Intel® Developer Zone
Nenhum conteúdo foi encontrado
Assine o Fóruns
Nenhum conteúdo foi encontrado

Tecnologia de virtualização Intel®

Intel® Xeon® Processor E5-2600 V3 Product Family Technical Overview
Por Sreelekshmy Syamalakumari (Intel)Publicado em 09/12/20140
Contents 1. Executive Summary2. Introduction3. Intel Xeon processor E5-2600 V3 product family enhancements.   3.1 Intel® Advanced Vector Extensions 2 (Intel® AVX2) Instructions   3.2 Haswell New Instructions (HNI)   3.3 Support for DDR4 memory   3.4 Power Improvements4. Grantley platform im...
Getting Kernel-Based Virtual Machine (KVM) to Work with Intel® Xeon Phi™ Coprocessors
Por loc-nguyen (Intel)Publicado em 05/29/20140
The current Kernel-based Virtual Machine (KVM) software does not recognize the existence of Intel® Xeon Phi™ coprocessors. In order to make the KVM recognize the coprocessors, we provide patches under the GPL license, to rebuild the kernel and qemu-kvm packages. The patches provided here are used...
Intel® SDK for OpenCL* Applications - Performance Debugging Intro
Por Maxim Shevtsov (Intel)Publicado em 11/08/20132
To the Intel® OpenCL SDK page Table of Contents 1. Host-Side Timing 2. Wrapping the Right Set of Operations 3. Profiling Operations Using OpenCL Profiling Events 4. Comparing OpenCL Kernel Performance with Performance of Native Code 5. Getting Credible Performance Numbers 6. Using Tools Download...
Loclville Case Study
Por adminPublicado em 04/24/20130
By John Tyrrell Download Article  Loclville Case Study.pdf [807.07 KB] Introduction Loclville is a free Windows* 8 app that provides an easy-to-use virtual community notice board. Developed by amateur app developer Zubair Lawrence, a Sr. Production Services Technician at Sony Pictures Imageworks,...
Assine o Artigos do Espaço do desenvolvedor Intel
Nenhum conteúdo foi encontrado
Assine o Blogs do Intel® Developer Zone
How to handle GUID_ZPixelFormats in graphics card driver with Direct3D DirectDraw and DXVA under XDDM
Por Letian Yi2
Hi all: I'm developing a virtual graphics card driver under XDDM. I have finished the DirectDraw part of the driver, and i can see the DirectDraw is enabled in dxdiag. Now i'm developing the D3D part, but when i handle GUID_ZPixelFormats in DdGetDriverInfo,  DirectDraw is disabled ! Does anyone know how to handle GUID_ZPixelFormats in DdGetDriverInfo ? My code: void DdInitZPixelFormats(PDD_GETDRIVERINFODATA lpGetDriverInfo) {     static const DDPIXELFORMAT g_zfmts[] =     {         {             sizeof(DDPIXELFORMAT), DDPF_ZBUFFER, 0,             { 16 }, { 0 }, { 0x0000ffff }, { 0x00000000 }, { 0x00000000 }         },         {             sizeof(DDPIXELFORMAT), DDPF_ZBUFFER, 0,             { 32 }, { 0 }, { 0x00ffffff }, { 0x00000000 }, { 0x00000000 }         },     };     DWORD num = sizeof(g_zfmts) / sizeof(DDPIXELFORMAT);     DWORD size = sizeof(g_zfmts);     UINT8 *buf = (UINT8 *)lpGetDriverInfo->lpvData;     memcpy(buf, g_zfmts, min(lpGetDriverInfo->dwExpe...
libiomp5md.dll missing
Por Bob H.1
Is there a way for me to compile a fortran executable that I will not get this error when I try to run it on other computers? Bob
Extremely slow guest/host after VMLaunch
Por roee l.4
Hey, I've been trying to run hypervisor on OSX 10.9 for a while and finally managed to set it up. Problem is that the CPU/CPUS I run the hypervisor on become extremely slow after VMLaunch. Everything seem right, I tested it using a simple user mode application which calls CPUID and the VM Exit handler I wrote successfully handles that. But the overall computer performance decreases significantly. The more cores I run VMLaunch on ,the slower it becomes. When run on all 4 cores I can't even move my mouse. What could it be?  The only VMExits I get are 'CPUID's which are probably done by the OS or some programs I use, but nothing else.  I hope that maybe one of you has experimented with it.   thanks!
vmlaunch fails - vm entry with invalid control field(s)
Por roee l.1
Hey. CPU Used :  Intel(R) Core(TM) i5-4258U CPU @ 2.40GH Operating system : OSX Mavericks 10.9.4 I looked at the source code of Bluepill , Xen and more. Got help there but still no luck =( Keep getting that error code 0x7 (Vm entry with invalid control field(s)). Here's the VMCS dump:
Can clflush evict any address
Por Younis A.1
Hi I'm wondering, can clflush instruction flush any type of addresses in a cache line (logica, linear or physical address) or has to be only a linear address. Thank you in advance for your help
issues with SR-IOV support in XL710 on Asus
Por Nobin M.0
I have a intel XL710 with four ports, lspci output is below 01:00.0 Ethernet controller: Intel Corporation Device 1572     Subsystem: Intel Corporation Device 0000     Flags: fast devsel, IRQ 16     Memory at <ignored> (64-bit, prefetchable)     Memory at <ignored> (64-bit, prefetchable)     Expansion ROM at f7780000 [disabled] [size=512K]     Capabilities: [40] Power Management version 3     Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+     Capabilities: [70] MSI-X: Enable- Count=129 Masked-     Capabilities: [a0] Express Endpoint, MSI 00     Capabilities: [e0] Vital Product Data     Capabilities: [100] Advanced Error Reporting     Capabilities: [140] Device Serial Number d0-6c-1f-ff-ff-ca-05-68     Capabilities: [150] Alternative Routing-ID Interpretation (ARI)     Capabilities: [160] Single Root I/O Virtualization (SR-IOV)     Capabilities: [1a0] Transaction Processing Hints     Capabilities: [1b0] Access Control Services     Capabilities...
Obtaining DRHD values for specific chipsets
Por Peter K.0
I have a problem with a specific BIOS (xw4600) that returns a DRHD with cap and ecap set to all ones, i.e. a broken BIOS, stopping VT-d from working. I know this is the manufacturer's responsibility, but I'm curious as to where these values are derived from. Obviously some are chipset specific, whilst others (error registers etc) appear to just be available (and probably not fixed) memory locations? The motherboard is X38 based. I've looked through the X38 Express datasheet and the ICH9 datasheet and cannot find the source of many of the values in the DRHD. Where are they defined, and if you're mad enough, is it possible to set up your own DRHD etc instead of using the BIOS (Obviously the DMAR table links to various RMRR and PCI ranges, but in this case there are a series of RMRR set up. If I assume those are correct it may be possible to fix the broken bits) The specifications are complex., and I'm probably missing some understanding, but I'm reasonably certain I'm lacking document...
how could i choose ept memory type?
Por water m.0
how could i chose ept memory type if the MTRR is disabled and the PAT is 0?
Assine o Fóruns
Nenhum conteúdo foi encontrado