Novas instruções AES
- Novas instruções Intel® AES (Intel® AES-NI)
Visão geral do Intel® AES-NI, um novo conjunto de instruções de criptografia, que melhora o algoritmo do AES (Advanced Encryption Standard - padrão de criptografia avançada) e acelera a criptografia de dados.
- Segurança na empresa com o Intel® AES-NI
Saiba por que a criptografia está com tudo no mercado hoje, principalmente nas empresas
- Instruções Intel® Advanced Encryption Standard (AES-NI)
Descrição das seis novas instruções que compõem o conjunto de instruções AES-NI e realizam várias partes de computação intensiva do algoritmo AES.
Gerador digital de números aleatórios
- Bull Mountain é o nome do código da Intel para sua nova instrução RdRand de arquitetura Intel® 64 e sua implantação de hardware do gerador digital de números aleatórios (DRNG). O Bull Mountain oferece uma solução de RNG baseada em processador, de alta qualidade e desempenho, com grande disponibilidade e segura.
Extensões da Instruction Set Architecture da Intel
- Intel® MPX (Intel® Memory Protection Extensions) é o nome das extensões da Arquitetura Intel® projetadas para aumentar a robustez do software
- Intel® SGX (Intel® Software Guard Extensions) é o nome das extensões da Arquitetura Intel® projetadas para aumentar a segurança do software por meio de um mecanismo de “inverse sandbox”
- As Intel® SHA Extensions (Intel® Secure Hash Algorithm Extensions) são uma família de sete instruções baseadas em Intel® Streaming SIMD Extensions (Intel® SSE) que são usadas juntas para melhorar o desempenho de SHA-1 e SHA-256 em processadores baseados na arquitetura Intel®
Por Jeff Kataoka (Intel)Publicado em 02/26/20131
White Paper: Deeper Levels of Security with Intel® Identity Protection Technology With the latest release in 2012 of Intel® Identity Protection Technology (Intel® IPT) introduced additional capabilities beyond the initial one-time password (OTP) solutions embedded in silicon and provided an exten...
Por Jeff Kataoka (Intel)Publicado em 02/22/20130
Safeguard Sensitive Information with Intel® Identity Protection Technology ( Intel® IPT ) Guarding personal identities and online accounts has become a major concern for consumers, business, government and institution as the threat from hackers and malware grows. Creating a simple, strong and se...
Por sukruth-v (Intel)Publicado em 02/12/20130
ntel® Static Analysis tool is capable of detecting around 250 different types of error conditions and can also detect race conditions resulting from misuse of parallel programming frameworks such as OpenMP* and Intel® Cilk™ Plus.
Por David Mulnix (Intel)Publicado em 12/18/20120
When one wishes to deploy Intel TXT in a cloud environment across a broad volume of systems the first requirement is enabling the technology within the BIOS on those systems. This article describes a methodology that will allow one to automate this process on Dell servers using Lifecycle Control...
Tecnologia de virtualização Intel®
- Resumo técnico de hardware de virtualização
A Tecnologia de virtualização Intel oferece amplo auxílio de hardware que acelera o desempenho de software de virtualização, melhora o tempo de resposta do aplicativo e oferece mais confiabilidade, segurança e flexibilidade.
- Virtualização: Uma amiga do desenvolvedor
Quanto mais os desenvolvedores usarem a virtualização, mais eles encontrarão novos usos para ela. Descubra o que está perdendo e como a virtualização pode ajudá-lo(a) a fazer muito mais.
- Tecnologia de virtualização Intel®: Animação em Flash*
Esta animação traz um panorama da Tecnologia de virtualização Intel®, que é uma técnica pela qual os recursos de hardware podem ser abstraídos, divididos e compartilhados entre vários ambientes de sistema operacional que são executados simultaneamente.
- Tecnologia de virtualização Intel®: Boas práticas para fornecedores de software
Esta série de artigos se destina a ajudar os desenvolvedores de software a ajustar seus aplicativos para o uso com a Intel VT.
Challenge Use Intel® Virtualization Technology in conjunction with other technologies to improve the Digital Home experience. The advent of Intel Virtualization Technology corresponds to another, even more significant hardware transition: multi-core processing. These two technologies complement...
Challenge Improve security in the Digital Home by means of virtualization. As powerful entertainment PCs take over more functionality in the Digital Home, it will become more important than ever to secure these platforms. This necessity is even more pronounced in those cases where the same PC b...
Challenge Hide the complexity of hardware from the operating system. Future microprocessors will need several levels of virtualization. For example, as shown in the figure below, virtualization is needed to hide the complexity of the hardware from the overlying software. The OS kernel and the s...
Optimizing DirectX* 8.0 Vertex Shaders Once again, welcome back to Maximum FPS! This month Ronen Zohar will provide us with a thorough understanding of how to take advantage of vertex shaders on Intel processors. Ronen is an Intel engineering manager from Haifa, Israel, and has worked closely wit...
Por Penny Svenkeson1
Hi all, In our hypervisor implementation, we can have multiple cores assigned to a single VM. In the multi-core VM configuration, we are seeing longer delays under virtualization for cores getting locks (even when there is no contention for the lock cell). If a core (or thread) has a guest cache line resident and takes a VMEXIT for some reason and another core want to get ownership of the guest cache line (for atomic operation), does the 2nd core have to wait for the VMRESUME on the first core before getting ownership? Are there any other reasons that would prevent a core from completing an atomic operation if other cores are in a VMEXIT condition? Core1 has cache line A Core1 takes a VMEXIT for timer interrupt Core2 tries a sync_fetch_and_add to cache line A <-- get ownership here Core1 does a VMRESUME <-- or wait till here for ownership Thanks for any insight. Penny
Not sure what forum would be most appropriate for this question, but this seemed close at least....kindly advise if there's a better place! For many years my company has been interested in the availability of cross compilation for Windows from Linux. Our primary development environment is Linux, and the various approaches to getting linux buildable software to build on windows involve various levels of pain and suffering of one sort or another. Being able to create native windows binaries without having to duplicate development environments would be a real benefit. Some level of capability in this regard has been available via the MinGW tools for at least a decade, and we used it for a time, but limitations such as inability to debug with ordinary windows tools were too much of a hinderance. Since we believe the claim that ICC is really the same compiler on Windows and Linux, it seems like it would be very straight-forward to create a Linux version of the compiler able to cr...
Por Yogi D.1
I am writing a thin hypervisor that allows 16-bit mode guests. The system boots into my 16-bit boot code which sets up 32-bit protected mode with identty mapped pages, then enables IA-32e compatibility mode and then switches into IA32e mode (64-bit). In this mode, the software sets up a hypervisor to allow unrestricted guests (this includes setting up EPT with proper caching controls refecting the cache setup via MTRRs). Then the software launches a 16-bit guest that runs well -- making BIOS calls for I/O services etc. All this is working quite well. However, I noticed a small discrepency in behavior when I press the power button. Before the 16-bit guest is launched, the system immediately shuts down when the power button is pushed. This also happens when the host mode is active (i.e., my code is processing a VM Exit). However, when the 16-bit mode guest is active, pushing the power button causes the machine to hang -- even the VM preemption timer does not cause a VM Exit. Be...
Por Tommy F.1
Hello can someone explain why intel vt-d is required for HVM ( fully virtualized VM) and not for Para-virtualized VMs. I know that in the pci-passthrough, the VM has control of the PCI. so the PCI needs to do DMA access to the VM memory, but as this is not possible, the PCI will tell the IOMMU about the virtual address, which will be converted to the physcial address in RAM, which corresponds to the VM memory. But what happens in case of Para-virtualization VM?
Por Yogi D.1
Hi. I am writing a small OS-agnostic hypervisor as a teaching tool for my students. The hypervisor code is loaded by the code I embed in a custom MBR on the boot device when the system boots. The hypervisor code switches to 32-bit proceted mode and then IA32e (64-bit mode, paged with identity mapping of linear -- physical addresses). It then sets up the 64-bit exception handling mechanism and tests of this exception handling mechanism are successful (CPL and DPL are 0 so no stack switching is expected). E.g., divide by 0, and page faults are handled as expected. Next, an IA32e mode guest is launched. The guest has its own paging tables (these are not identity mapped). The guest handles exceptions and interrutps by itself (i.e., it has a different IDT than the host, and the exception bitmap control is set to 0). All this is working. External interrupts, exceptions, memory accesses, access to I/O devices is working well int he guest. The guest exits to the host because of va...
Por David K.0
With the help of Virtual Services, we can start of the software development life cycle. But I have one question in mind can we follow in all Development like Custom, Website and Mobile Application Development?