(Вы можете скачать PDF-версию этой статьи во вложении.)
This document gives platform designers, thermal engineers, hardware engineers, and computer architects instructions on how to acquire idle power readings from the Intel® Xeon Phi™ coprocessor.
I don’t know if any of you have noticed but Intel® has a tendency to emphasize its own homegrown tools. This isn’t bad as Intel has some of the best. Still, if someone has a favorite hammer, there’s a tendency to use that hammer for just about everything.
How about the future? Have we reached the pinnacle of power management?
INTRODUCTION AND PURPOSE:
This article endeavors to provide a single point of reference to Power Management blogs, articles and other resources relevant to the Intel® Xeon Phi™ coprocessor.
Unlike a lot of previous recent blogs, this series is about power management in general. At the very end of the series, I’ll write specifically about the Intel® Xeon Phi™ coprocessor.
I have talked incessantly over the years about power states (e.g. P-states and C-states), and how the processor transitions from one state to another. For a list of previous blogs in this series, and well as other related blogs on power and power management, see the article at [List0]. But I have left out an important component of power management, namely the policy.
(For a PDF version of this article, download the attachment.)
At SC13 (Super Computing 2013)*, someone commented that Intel seems to have some super-secret set of tricks in its pocket, allowing us to optimize “far beyond those of mortal man”+. We don’t really have any super-secret tricks. Even if we did, we wouldn’t use them. We want mortal man (you) to be able to reproduce whatever we do. It is also in our business interest to insure that you can optimize on Intel hardware to the fullest extent possible.
I just wanted to let whoever is listening that I just published updates to the Resource Guide for Intel® Xeon Phi™ Coprocessor Developers and Resource Guide for Intel® Xeon Phi™ Coprocessor Administrators documents.