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Introduzione a Intel Perceptual Computing SDK: Face Landmarks e Face Pose

In questo articolo ci occuperemo di come utilizzare le API messe a disposizione da Intel Perceptual Computing SDK per il recupero dei Face Landmark e Face Pose.

Cosa sono i landmark e le pose

Si definiscono Face Landmark una serie di punti (detti marker) ben definiti sulla faccia umana. Ad esempio la punta del naso o l'angolo della bocca. Si definisce Face Pose, invece, la posizione di un viso nello spazio in termini di inclinazione dello stesso lungo i tre assi cartesiani.

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  • Intel Perceptual Computing SDK 2013 get GOLD release 2

    In these days our loved Perceptual SDK receive an update in the SDK incarnation, there's a lot of improvement and new implementation.

    The release is marked with the version number 8779, just from the change log we can note the news.

    First of all the Java app dev support and Projection in framework porting libraries support was added,

    Many of the samples (either C++ and C#) was rewritten or heavily modified.

    Introduzione a Intel Perceptual Computing SDK: Face Detection

    In questo articolo ci occuperemo di Face Detection ed in partcolare delle funzionalità messe a disposizione dal Perceptual Computing SDK.

    Cosè il face detection

    Face detection è una tecnologia informatica che determina le posizioni e le dimensioni di volti umani all'interno di immagini (o di video). La tecnologia rileva le caratteristiche facciali e ignora tutto il resto, come edifici, alberi, corpi.
    Più in generale, Face Detection è un caso specifico della tecnologia che va sotto il nome di Object-Class Detection (dove la classe di oggetto è il volto umano).

  • Desenvolvedores
  • Parceiros
  • Professores
  • Estudantes
  • Microsoft Windows* (XP, Vista, 7)
  • Microsoft Windows* 8
  • Windows*
  • .NET*
  • Principiante
  • SDK da computação perceptiva Intel®
  • Computação perceptiva
  • Intel Perceptual Computing SDK
  • VB.NET
  • Microsoft Visual Studio* 2012
  • Troubleshooting HOWTO: Bad hardware? MPSS? Configuration?

    Are you having problems with your hardware (Cannot see your Intel(R) Xeon Phi(tm) coprocessor?  Sporadic accessibility?) or with the Intel(R) Manycore Platform Software Stack (Intel(R) MPSS) running reliably?

    Attached to this post is a PDF "flowchart" that explains how you can troubleshoot the problem (note:  this applies if you are running the Linux* operating system on your host), and shows what information you will want to collect if you need to escalate your issue to your OEM provider or Intel.

    What collateral/documentation do you want to see?

    Do you have questions that you are not finding the answers for in our documentation?  Need more training, source code examples, on what specifically?   Help us understand what's missing so that we can make sure we develop documentation you care about (what is important, and what is nice to have)!   Thank you

    FAQS: Compilers, Libraries, Performance, Profiling and Optimization.

    In the period prior to the launch of Intel® Xeon Phi™ coprocessor, Intel collected questions from developers who had been involved in pilot testing. This document contains some of the most common questions asked. Additional information and Best-Known-Methods for the Intel Xeon Phi coprocessor can be found here.

    The Intel® Compiler reference guides can be found at:

    Баги и фичи

    Уважаемые читатели и авторы русскоязычных блогов Сообщества Разработчиков Intel, с сентября 2012 года блоги работают на новой площадке - Intel Developer Zone (IDZ), используют новый "движок", дают новые возможности, и, к сожалению,.... новые баги. Так, в течение нескольких недель вместо русскоязычных блогов на соответствующей странице IDZ отображались блоги на английском языке, а RSS-подписчикам однажды даже довелось получить посты на китайском языке. Существуют проблемы и с отображением блогов и с их созданием. Хотя их число постепенно и неуклонно уменьшается, но пока оно больше нуля.

    GFlops on MIC

    Hello Intel,

    I wrote "a kind of" meta compiler to generate SIMD code on multi platform (x86, power, PHI, etc ...). I will present my work in the ISC 2014 in june. I am preparing the Super Computing conference, where I would like present to result on the Phi platform I have an issue.

    I am trying to calculate the GFLOP/s of my application, a first approach will be to count the number of operations and divide by the elapsed time, as usually done for dgemm benchmark. Unfortunately I have thousands of lines ...

    performance issue of operating on overlap area between two arrays

    Hi, My application program needs a lot of operators (copy/accumulate...) on two arrays' overlap. In most cases, the overlap area is not very large. A typical size is 100x100*2.  I have made a simple benchmark for these functions in the attached file.

    Unfortunately, I found the performance on MIC is much poor than Xeon CPU. For all three cases, one OpenMP thread is the best. 

    Offload: 0.026 seconds

    Native: 0.018 seconds

    CPU: 0.0009 seconds 

    Any suggestion on improving performance on MIC. Can we achieve better performance on MIC than that on CPU?

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