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In the period prior to the launch of Intel® Xeon Phi™ coprocessor, Intel collected questions from developers who had been involved in pilot testing. This document contains some of the most common questions asked. Additional information and Best-Known-Methods for the Intel Xeon Phi coprocessor can be found here.
The Intel® Compiler reference guides can be found at:
- Intel Instruction Set Architecture Extensions
- Intel® Architecture Instruction Set Extensions Programming Reference includes:
- Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions (AVX512F, AVX512DQ, AVX512BW, AVX512VL, AVX512CD, AVX512PF, AVX512ER)
- Intel® Secure Hash Algorithm (Intel® SHA) extensions
- Intel® Memory Protection Extensions (Intel® MPX)
Looking at the new version of Volume 2 of the SDM (document 325383-055), I just noticed that the "Description" field for the VINSERTF128 instruction (page 4-514) is incorrect. It appears to have been copied (with some modification) from the description of the VINSERTPS instruction (which is described with the INSERTPS instruction on page 3-422), but it should be almost identical to the description of the VINSERTI128 instruction on page 4-515.
In the last release 55 of Intel® 64 and IA-32 Architectures Software Developer’s Manual in Vol 2C A-11, we can't see MPX instructions. In fact, I usually use opcode maps to find instructions encoding. I am not sure this forum can be used to report typos like these. Just tell me if I am not in the right place.
I have been running a program where precision of doubles mean a lot to my program.
However due to some strange reason it seems like Xeon phi is rounding off a few bits(at 10^-8th bit) and this seems to be causing some instabilities to my model. A small round off error grows over my model over iteration of time step and my model fails to converge.
here is some sample differences in error.
Xeon phi value