offload_transfer: array of variables?


I would like to pre-allocate a number of buffers for later data transfers from CPU to MIC, using explicit offloading in C++.

It works nicely if each buffer corresponds to an explicit variable name, as e.g. in the double-buffering examples. However, I would like to have a configurable number of such buffers (more than 2), i.e. an array of buffers. (the buffers are used for asynchronous processing on the MIC, and I need quite a few of them).

SGX support removed from Intel's ARK website?

Hi Intel


Until recently (1-2 weeks ago), Intel's ARK website listed SGX as being supported on the new Skylake 6600K and 6700K processors. However, this information now seems to have been removed? The page I'm talking about is (for the 6700K):

So does this mean SGX is no longer supported on these processors?



Efficiently Use KNC Instructions on Unaligned Data

MIC requires strict 64Byte data alignment to utilize vpu, but why? I found Sparc also have such an requirement. But other multi-core CPU can handle unaligned data.

As MIC can automatically vectorize a for loop of data(with compiler optimization), what if the data is unaligned in this case? will the auto optimization still work?  if yes, how?


I would like to clarify my problem here.

Knight's Landing + Java

Dear Intel Staff,

I just got to know some details of your great presentation of Knight's Landing (KNL) at Hot Chips this year. Information about KNL on the website is still sparse. From your slides I understand that there will be a version of KNL that is socked and can be used as a primary CPU in a rack. However, this raises quite some questions that I cannot find satisfying answers.

Assine o Servidor