Intel® Advanced Vector Extensions

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  • NRI
  • Intel® AVX2
  • OLTP
  • NUMA
  • Intel® Advanced Vector Extensions
  • Big Data
  • Vetorização
  • Fast Gathering-based SpMxV for Linear Feature Extraction

    This algorithm can be used to improve sparse matrix-vector and matrix-matrix multiplication in any numerical computation. As we know, there are lots of applications involving semi-sparse matrix computation in High Performance Computing. Additionally, in popular perceptual computing low-level engines, especially speech and facial recognition, semi-sparse matrices are found to be very common. Therefore, this invention can be applied to those mathematical libraries dedicated to these kinds of recognition engines.
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  • Windows*
  • C/C++
  • Intermediário
  • Intel® Advanced Vector Extensions
  • Extensões Intel® Streaming SIMD
  • Sparse Matrix-Vector multiplication
  • sparse matrix
  • Feature Extraction
  • speech recognition
  • Processadores Intel® Core™
  • Otimização
  • Computação paralela
  • Vetorização
  • SGX extensions



    With the new SGX extensions available in the new Skylake based CPU's (6700K and 6600K) I was wondering if Intel is ready to release more information about these technologies. Specifically:


    1) Is there any plans for an emulator that can be used to emulate these technologies?

    I210 driver delevopment (DOS)


    I currently try to adapt firmware to new hardware. And have problems to get the I210 ethernet controler fetching DMA packets.

    Old system: AMD Geode SC1200 Processor + Intel 82551
      - Firmware is a Win32 application using DOS + DOSExtender(DPMI)
      - The Intel 82551 Controller is directly controlled by firmware (NO DOS TCP/IP SOCKET)

    Switching to protected mode clarification


    I'm trying to understand a line in the Intel Architecture manual. It's a description of a possible failure situation when switching to protected mode.

    Section 9.9.1 gives a recommended procedure for switching to protected mode. Step 3 is the mode switch, and step 4 is to immediately make a far transfer to initialize CS and cause serialization. The final paragraph says failures can occur if there are instructions between steps 3 and 4.

    No explanation of comparison codes for integer vector compare instructions

    In the ISE document 319433-022, instructions such as VPCMPD refer to an imm8 operand as a comparison predicate.  However, there is no explanation of the values of the predicate.

    The Operation section of the instruction doc does indicate the 8 values of the low 3 bits.  But I only noticed this by chance.  It would be nice to have something in the Description section to refer the reader to the details.  Actually, why not use a similar language to that for VCMPPS, etc.

    Wrong memory size for VGATHERQPS (?)

    My version of the document, 319433-022, page 350 shows

    EVEX.128.66.0F38.W0 93 /vsib
    VGATHERQPS xmm1 {k1}, vm64x

    I think this should be vm32x, not vm64x, since the operands are single-precision floats.

    Similarly for the other two encodings of this instruction.

    Please check other gather/scatter instructions that they are correct also.


    What is syntax for broadcast decorator?

    The ISE doc only describes the decorator syntax with the single example {1to16} (document 319433-022 page 7).

    I would assume that generally you write {1ton} where n = the full vector size / the single element size.  But it would be nice to specify this exactly.

    However, GNU `as` will not accept {1to4] or smaller.  Furthermore, it does not accept a broadcast decorator with a 128- or 256-bit vector size.  If I use .byte to assemble 128- and 256-bit instructions, the disassembler shows the {1to8} or {1to16} decorator regardless of VL.  Example:

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