Hi, I have an assignment for my computer architecture class.
I have read intel's Architecture Optimization Manual and still cannot find the answer.I need to know how many bytes of Instructions are removed from the L1 instruction cache.
Say I run a FFT sequence/pr, it is of say X bytes.
1.Are X bytes, cached as whole in the L1 cache or it is partially cached?
2. Are the X bytes fully(wholly) transmitted to the L2 cache?
3. Does the same procedure 1 and 2, hold, when FFT program/Sequence is removed?