Processadores Intel® Itanium®

BKMs on the use of the SIMD directive

We had an ask from one of the various “Birds of a Feather” meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences. The customer wanted to know BKMs (Best Known Methods) on the proper usage of the new OpenMP* 4.0 / Intel® Cilk™ Plus SIMD directive. I volunteered to create such a list. Investigating the topic more thoroughly, I discovered that there is already a vast amount of resources on vectorization and the use of the SIMD directive.

优化联网待机状态下WINDOWS 8 应用程序

这篇白皮书介绍了如何测试和分析软件在Windows待机连接状态下的行为。同时还介绍了如何发现待机连接状态下影响电量的根本原因以及如何优化。这篇白皮书旨在面向 ISVs, OEMs, 和其他技术相关人士。
  • Desenvolvedores
  • Desenvolvedores Intel AppUp®
  • Parceiros
  • Microsoft Windows* 8.x
  • Windows*
  • Avançado
  • Depuração
  • Processadores Intel® Core™
  • Processadores Intel® Itanium®
  • Área de trabalho do Microsoft Windows* 8
  • Estilo de interface do Microsoft Windows* 8
  • Otimização
  • Eficiência energética
  • Black Belt Itanium® Processor Performance: Use of Constrained Event Collection (Part 4 of 5)

    by David Levinthal


    Introduction

    This paper, fourth in a series of five articles on optimizing software for the Itanium® processor family, focuses on the sources of execution inefficiency and how they can be converted into optimization opportunities. For an introduction to this topic and additional information see the other parts of this series:

  • Processadores Intel® Itanium®
  • Black Belt Itanium® Processor Performance: Performance Monitoring Capabilities (Part 2 of 5)

    by David Levinthal


    Introduction

    This paper, second in a series of five articles on optimizing Itanium® processor family software, focuses on the unprecedented performance monitoring capabilities of the Itanium® processor. The future articles will cover data blocking and multi level caches, the use of opcode matching and data ear events in performance analysis, visual inspection of assembler in the Intel® VTune™ analyzer and a variety of other topics. See the other parts of this series for more information:

  • Processadores Intel® Itanium®
  • Black Belt Itanium® Processor Performance: Data Blocking and Multi Level Cache Usage (Part 3 of 5)

    by David Levinthal


    Introduction

    This paper, third in a series of articles on optimizing Itanium® processor family software, focuses on graphics-intensive and other High Performance Computing applications. The future articles will cover the use of opcode matching and data ear events in performance analysis, visual inspection of assembler in the Intel® VTune™ analyzer and a variety of other topics.

  • Processadores Intel® Itanium®
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