Intel® Performance Tuning Utility (Archived)

DRAM Row Buffer Page Policy


   I am working on a SandyBridge Processor.

   I want to change the row-buffer management policy of IMC.

   Currently It uses a closed page policy. I know that IMC uses

   an adaptive paging policy.

    But I want to make it open page. The only option I could think of

    is writing to the PCI Device Register which has a configurable

    Bit set for choosing Paging Policy. But doing it online will be stupid.

    My Bios does not have any option for such a change. The only

Overhead of Last Branch Record

Hi folks,

a) Can you give a rough idea of how much LBR slows down program execution of common programs - both CPU and IO intensive ? I could not see any substantial overhead (~2-5%) with LBR turned ON for some microbenchmarks.

b) Is branch prediction mechanism turned OFF when LBR tracing is ON ?

Thanks !

Classifying D-TLB misses using Data access profiling

Hello,I need to estimate amount of DTLB misses that are to heap region versus those due to accesses to stack region. In the user guide of the PTU the Data Access Profiling section (2.5) mentions that PTU can figure out linear address of an memory operand for an event. If linear address of an event can be found then it seems possible to figure out whether the access goes to dynamically allocated region or not. However, I am not really clear how can I use this facilty of PTU to calssify the DTLB misses as mentioned above. Can any body provide me some leads on this?ThanksArka

What is supposed to happen when you start the auto-tuner?

So I've been having trouble OCing this new machine, its a p67 intel board with a i5 2500k. Changing the settings manually in bios seems to have no effect, so I'm trying the auto tuner.After starting it however, all that happens is the pc reboots, fans churn for a second, it beeps once, and starts over. I thought maybe it was part of the process, but it has been doing that for about 2 hours now, with no change.Doesn't seem like that should be normal...

Statistics About QPI

Hi there,I am working on a project related to QPI. We need to collect some statistics. There are two CPUs (CPU A and B) connecting to each other with a QPI. Each CPU has direct accesses to a RAM, a SSD and a Niantic. It is possible that CPU A wants to access RAM B which connects to CPU B. The data path is:CPU A => CPU B (through QPI) => RAM B.The statistics we need is: Time{CPU A access RAM B} / Time{CPU A access RAM A}.There are some other statistics that we are interested for this topology setup, but basicall the above example shows what we need.

questions about performance monitoring counters

Hi all, I am a newbie to Intel forum. I hope this is the correct subforum to post this thread; if not, please forward it to the correct place. I am working on a project using hardware performance monitoring counters. In my current implementation, the counter values are read through a file under /proc (thus I need to create a proc_entry before the sampling and read the values to this file during execution), and the samplings are implemented by inserting a task into the delayed work queue.

"Show Utility Chart" - Explanation


Regarding the charts available from "Show Utility Chart" in Memory Hotspots view:

- the Access Stride Distribution

- the Working Set

- the Array of Structures

I could not find their description in the User Guide, so would appreciate if you could let me know what the X and Y axes represent (and if by default they use data from the whole experiment as it seems), and the purpose of each chart.



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