Intel ISA Extensions

Resources about Intel® Transactional Synchronization Extensions (Intel TSX)


you might find this collection of technical material about Intel TSX instructions useful:

By a suggestion from some senior forum contributors I am making this post sticky.

Best regards,


Links to instruction documentation

How long does a 6700K take to multiply two integers?


I just read on Wikipedia that an IBM 1620 took 17ms to multiple two integers, and I was wondering how long a modern CPU takes to execute the same operation.

I hope I'm in the right forum. I found this question from 2008 ( ), which, going by Google, seems to suggest that I should ask my question here.

Regardless, I'm looking forward to your answers.

How to avoid unsupported instructions?

I compile this inline asm line with Intel compiler:

  vpxor  ymm0, ymm0, ymm0

compiles ok, but is an AVX2 instruction, that will not run on my older i5 CPU and give an illegal instruction exception.

How can I tell the compiler to disable specific SIMD instructions? E.g. like this: /disable:AVX2 ?

Do Non-Temporal Loads Prefetch?

I can't find any information on this anywhere. Do non-temporal load instructions (e.g. MOVNTDQA), which use the separate non-temporal store rather than the cache hierarchy, do any prefetching? How does the latency and bandwidth compare to a normal load from main memory?

Is the way to think about the store as if it is as "close" to main memory as the L3 cache, but also as "close" to the register files as the L1 cache?

Possible bug in SDE - jump with 16-bit operand size

The Software Developer's Manual, and the corresponding AMD document, indicate that after the new RIP is calculated, it is then truncated to whatever the instruction's operand size is.

To see if this was actually true, I assembled a JMP instruction with a 66 prefix, to set an operand size of 16 bits.  I would expect this to jump to a 16-bit address.

Running this instruction on my AMD Steamroller CPU, I got a segmentation fault.

But running it with SDE, the trace shows a jump without truncating the destination address.

It would appear that SDE is incorrect.

Launch Key and EINIT Token

The SGX Extensions Programming Reference, page 12, states that "The EINIT token is used by EINIT to verify that the enclave is permitted to launch." Some field in the EINIT token are MACed using Launch key, however, there seems to be a chicken-and-egg problem. Unless the enclave has called EINIT, the enclave is not operational yet, so calling EGETKEY for LaunchKey will return error. On the other hand, in order to compute the EINIT-Token CMAC, one need access to the launch key!!!

SGX support


I'm a graduate student who wants to utilize Intel SGX instructions. I heard that the new CPUs, which include Intel SGX instructions, will be released by 26th Oct, 2015. [1] And I'd like to buy one of them. 

Q1. Do I have to need a motherboard which contains a BIOS supporting configuration for SGX? (enable/disable SGX and/or adjusting Enclave memory size)

Q2. If I do so, which motherboards can I buy?


Best Regards,


Byungkwon Choi


* Reference

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