‹ Retornar à série de vídeos: Recorded Training Series

Part 1: Introduction to Intel® Xeon and Xeon Phi™ Architectures

  • Visão geral

In episode 1 of the “Hands-On Workshop (HOW) series on parallel programming and optimization with Intel® architectures”, we introduce Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors and discuss their features and purpose.

We also begin our introduction to portable, future-proof parallel programming and discuss the pre-requisites for high performance on the Intel® Many Integrated Core Architecture (Intel® MIC Architecture):

• Thread parallelism
• Vectorization
• The optimized memory access pattern

The episode introduces the native model for programming Intel Xeon Phi coprocessors that allows us to re-use application code designed for general-purpose CPUs.

The hands-on part of the episode demonstrates how the Linux* operating system (OS) on the host inter-operates with the OS on coprocessors, and how to use Intel compilers to run native applications on coprocessors.