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Think Parallel Modern Applications for Modern Hardware

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High performance computing (HPC) codes have used MPI and similar models to scale to multiple nodes, but increasingly parallelism is also required within a node, and even within a single core. Application programmers must be prepared to address parallelism at the message passing, threading, and SIMD layers. Upon completion of this webinar you will become familiar with modern Intel parallel architectures and Intel® Xeon Phi™ architecture for both hardware and software.