Expectations for User Source Code Changes


Although most codes can run in the Intel® Many Integrated Core Architecture (Intel® MIC Architecture) with little to no changes, to run EFFICIENTLY may require changes in user source code. This chapter examines algorithmic some general topic related to user source code changes that can enable applications to get optimal efficiency.


One reason for sub-optimal application performance may be that the code is bound by memory bandwidth. This may occur, for instance, if the code is not blocked for cache hierarchies, resulting in cache misses. Another reason may be that the code gets only partially vectorized due to irregular memory accesses. To improve performance in such cases, programmer intervention in the form of algorithmic changes is required. You can find more details of such algorithmic changes in the following paper:

ISCA 2012 Paper: Can Traditional Programming Bridge the Ninja Performance Gap for Parallel Computing Applications? (June 2012)

The next several chapters in this guide will touch on a few key ways to help remove memory bandwidth constraints.

Take Aways

Memory bandwidth constrained codes will exhibit poor performance.  User source code changes, if possible, can remove some of these bottlenecks and help the compiler do a better job of optimizing your application.


It is essential that you read this guide from start to finish using the built-in hyperlinks to guide you along a path to a successful port and tuning of your application(s) on Intel® Xeon Phi™ coprocessors.  The paths provided in this guide reflect the steps necessary to get best possible application performance.

BACK to Preparing for the Intel® Many Integrated Core Architecture (Intel® MIC Architecture)

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