Code Modernization Best Practices: Multi-level Parallelism for Intel® Xeon® and Intel® Xeon Phi™ Processors
Intel® Xeon® and Intel® Xeon Phi™ processor based platforms provide multiple levels of parallel execution resources. The amount of compute power of these resources is growing with every product generation, yet most applications do not fully utilize the available computing resources. This session will provide details on the growth in hardware resources and characterize performance using different levels of parallelism. Also covered are the key principles of how to use all levels of parallelism with clear examples and supporting data.
- Parallel computing resources in Intel® Architecture (IA)
- The parallel programming model for IA
- Best practices in parallelizing serial code
- The limitations of performance portability
Speaker: Robert Geva Principal Engineer, Manager of Financial Services Engineering Group, Intel Corporation