Documentation for uncore performance monitoring units

Hello everyone,

The uncore performance monitoring units (uncore PMUs) provide many useful information like memory controller traffic, traffic between sockets/processor packages, energy related metrics in the uncore (sleep states for Intel® Quick Path Interconnect links or DRAM sleep states for example). These metrics can be used in tools for system and platform analysis.

The documentation for uncore performance monitoring units for various Intel processors is distributed over different documents. In this blog I will try to summarize the links to the corresponding documents that should help searching for the correct document.

Intel® Core™variousmemory traffic, last level cache (CBO) events in SDM (chapter 18 Performance Monitoring)
Intel® Xeon® Scalable Processor Skylake-SPthis uncore PMU guide
Intel® Xeon® E5 and E7 v4 series Broadwell-EP and Broadwell-EXthis uncore PMU guide
Intel® Xeon® D-1500 series Broadwell-DEthis uncore PMU guide
Intel® Xeon® E5 and E7 v3 series Haswell-EP and Haswell-EXthis uncore PMU guide
Intel® Xeon® E5 v2 and E7 v2 series Ivybridge-EP and Ivybridge-EXthis uncore PMU guide
Intel® Xeon® E7 series Westmere-EXthis uncore PMU guide
Intel® Xeon® E5 series SandyBridge-EP (Jaketown)this uncore PMU guide
Intel® Xeon® 7500 series Nehalem-EXthis uncore PMU guide


I hope this summary can help you.


Best regards,


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