The Intel® Xeon Phi™ Product Family x200 series processors (formerly known as “Knights Landing”) contain a model specific feature, which allows the MONITOR and MWAIT instructions to be executed in rings other than ring 0, whereas architecturally these instructions are restricted to ring 0 (kernel code). Specifically, this feature allows them to be executed in ring 3, which is normal user-mode.
The feature can be enabled by setting bit 1 (as below) in MSR 140H (the MISC_FEATURE_ENABLES model-specific register). The register can also be read to determine whether the instructions are enabled at other than ring 0.
|Address||Register Name||Scope||Bit Description|
|1||If set to 1, the MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state other than C0 or C1, the instruction operates as if EAX indicated the C-state C1.|
Experimenting with this now
To experiment with this feature before kernels are enabled, you can use the rdmsr and wrmsr commands from the MSRTools package .
Look at the state of each logical CPU
% sudo rdmsr –a 0x140 0 0 0 ... A total of 272 lines of output on a 68 core machine ...
To enable the feature, write the appropriate bit (if any of the reserved bits were set, you should preserve them; here they were not).
% sudo wrmsr –a 0x140 2 % sudo rdmsr –a 0x140 2 2 2 ... A total of 272 lines of output on a 68 core machine ...
All users of the machine can now execute user-level code that uses the MONITOR and MWAITinstructions without that causing an invalid-opcode exception (which in turn appears as a SIGILL signal on Linux).
 Full details of MONITOR and MWAIT can be found in the Intel® 64 and IA-32 Architectures Software Developer Manual