The Intel® Xeon Phi™ Product Family x200 series processors (formerly known as “Knights Landing”) contain a model specific feature, which allows the MONITOR and MWAIT[1] instructions to be executed in rings other than ring 0, whereas architecturally these instructions are restricted to ring 0 (kernel  code). Specifically, this feature allows them to be executed in ring 3, which is normal user-mode.

The feature can be enabled by setting bit 1 (as below) in MSR 140H (the MISC_FEATURE_ENABLES model-specific register). The register can also be read to determine whether the instructions are enabled at other than ring 0.

Experimenting with this now

To experiment with this feature before kernels are enabled, you can use the rdmsr and wrmsr commands from the MSRTools package [2].

Look at the state of each logical CPU

% sudo rdmsr –a 0x140
0
0
0
... A total of 272 lines of output on a 68 core machine ...

To enable the feature, write the appropriate bit  (if any of the reserved bits were set, you should preserve them; here they were not).

% sudo wrmsr –a 0x140 2
% sudo rdmsr –a 0x140
2
2
2
... A total of 272 lines of output on a 68 core machine ...

All users of the machine can now execute user-level code that uses the MONITOR and MWAITinstructions without that causing an invalid-opcode exception (which in turn appears as a SIGILL signal on Linux).