When the option to use multiple PCIe* endpoints is needed, asynchronous vs synchronous communication must be determined. In the cases where synchronous communication is required, a packet switch may be the ideal solution. While more expensive than the previous solutions, packet switches have the built-in logic to control multiple PCIe lanes for simultaneous communication. Packet switching splits the PCI-Express datapath at the network level in the OSI model, offering greater flexibility to communicate to PCI-Express endpoints synchronously.

If asynchronous communication is desired between multiple PCI-Express endpoints, a PCI-Express MUX provides the necessary connectivity.  A fanout buffer is required for output control of asynchronous endpoint devices.

Multiple Asynchronous PCI-Express Endpoints

The diagram below shows how to connect multiple PCI-Express devices communicating asynchronously via PCI-Express MUX.

 

Notes:
  1. Hardware based solution that supports 1 USB3 or multiple asynchronous PCI-Express based endpoints. The PCI-Express interface is designed
    for multiple asynchronous Mini-PCI-EXPRESS based connectors.
     A resistor stuffing selects which interface is used (USB3 or PCI-Express).
  2. Block diagram shows use of PCI-Express Port 1; usage of Port 0 is not supported.
  3. The PCI-Express sideband signals (CKLREQ, WAKE, PERST) are omitted in the example for clarity.

Multiple Synchronous PCI-Express Endpoints

The following diagram shows how to connect multiple PCI-Express devices communicating synchronously.

 

Notes:
  1. Hardware based solution that supports 1 USB3 or multiple synchronous PCI-Express based endpoints. The PCI-Express interface is designed
    for multiple synchronous Mini PCI-Express based connectors. A resistor stuffing selects which interface is used (USB3 or PCI-Express).
  2. Block diagram shows use of PCI-Express Port 1; usage of Port 0 is not supported.
  3. The PCI-Express sideband signals (CKLREQ, WAKE, PERST) are omitted in the example for clarity.

 

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