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Article

Designing the Framework of a Parallel Game Engine

How to Get the Most Out of a Multi-Core CPU with Your Game Engine
Автор: Последнее обновление: 12.12.2018 - 18:00
Article

OpenMP* and the Intel® IPP Library

How to configure OpenMP in the Intel IPP library to maximize multi-threaded performance of the Intel IPP primitives.
Автор: Последнее обновление: 31.07.2019 - 14:30
Article

Benefitting Power and Performance Sleep Loops

This article provides recommendations to improve performance and limit power consumption of multi-threaded applications on multicore processors.
Автор: Joe Olivas (Intel) Последнее обновление: 08.07.2019 - 15:07
Article

Case Study: Parallelizing a Recursive Problem with Intel® Threading Building Blocks

Intel worked closely with DreamWorks Animation engineers to improve the performance of a key rendering system library by up to 35X performance improvement in some cases.
Автор: Louis F. (Intel) Последнее обновление: 10.07.2019 - 16:59
Article

Improving Averaging Filter Performance Using Intel® Cilk™ Plus

Intel® Cilk™ Plus is an extension to the C and C++ languages to support data and task parallelism.  It provides three new keywords to i

Автор: Anoop M. (Intel) Последнее обновление: 12.12.2018 - 18:00
Article

哈工大计算机网络实验一 :多线程服务器编程

思路:linux下包含头文件#include <pthread.h>

编译的时候加上参数 -lpthread

Автор: Последнее обновление: 05.07.2019 - 14:10
Article

Vectorizing Loops with Calls to User-Defined External Functions

Introduction

Автор: Anoop M. (Intel) Последнее обновление: 12.12.2018 - 18:00
Блоги

The switch() statement isn't really evil, right?

In my current position, I work to optimize and parallelize codes that deal with genomic data, e.g., DNA, RNA, proteins, etc.

Автор: Clay B. (Blackbelt) Последнее обновление: 04.07.2019 - 10:46
Article

Debugging Intel® Xeon Phi™ Applications on Linux* Host

Read details about a debug solution for Intel® Many Integrated Core Architecture (Intel® MIC) that can debug applications running on an Intel® Xeon Phi™ coprocessor.
Автор: Последнее обновление: 06.07.2019 - 16:40
Article

Disclosure of Hardware Prefetcher Control on Some Intel® Processors

This article discloses the MSR setting that can be used to control the various hardware prefetchers that are available on Intel processors based on the following microarchitectures: Nehalem,

Автор: Vish Viswanathan (Intel) Последнее обновление: 05.07.2019 - 20:34