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How to manually target different Intel® Core™ processors, Intel® Xeon® processors and Intel® Xeon Phi™ processors

Manual cpu dispatch may be used to write code that will be executed only on Intel processors such as 2nd generation Intel® Core™ processors (formerly code named “Sandy Bridge”) and 3rd generation Intel® Core™ processors (formerly code named "Ivy Bridge") with support for Intel® Advanced Vector Extensions, or 4th generation Intel® Core™ processors (formerly code named "Haswell"), 5th generation...
Автор: Martyn Corden (Intel) Последнее обновление: 21.03.2019 - 12:40
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Using HLE and RTM with older compilers with tsx-tools

To use HLE/RTM to improve lock scalability the lock library needs to be enabled.

Автор: Andreas Kleen (Intel) Последнее обновление: 14.06.2017 - 13:26
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TSX fallback paths

The need for fallback paths
Автор: Andreas Kleen (Intel) Последнее обновление: 14.06.2017 - 13:26
Article

How to detect New Instruction support in the 4th generation Intel® Core™ processor family

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Автор: Max Locktyukhin (Intel) Последнее обновление: 04.02.2019 - 15:50
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Transactional memory support: the speculative_spin_mutex

Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transaction

Автор: Последнее обновление: 28.05.2018 - 18:30
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Transactional Memory Support: the speculative_spin_rw_mutex (Community Preview Feature)

In a previous post I discussed the Intel® Tra

Автор: Последнее обновление: 14.06.2017 - 15:46
Article

TSX anti patterns in lock elision code

Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.

Автор: Andreas Kleen (Intel) Последнее обновление: 07.06.2017 - 10:53
File Wrapper

Parallel Universe Magazine - Issue 17, March 2014

Автор: админ Последнее обновление: 21.03.2019 - 12:00
File Wrapper

Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture

Автор: админ Последнее обновление: 15.05.2018 - 11:30