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Article

16bit 3D Convolution: SSE4+OpenMP implementation on Penryn CPU

Attached presentation describes SSE3/SSE4 implementation of 3D Convolution for 16bit original data.

Автор: Zvi Danovich (Intel) Последнее обновление: 09.03.2019 - 12:30
Article

Intel® IPP - Threading / OpenMP* FAQ

This page contains common questions and answers on multi-threading in the Intel IPP.
Автор: Последнее обновление: 31.07.2019 - 14:30
Article

Intel® IPP - Using Intel® IPP in Java* applications

More Information about using Intel® IPP in Java* applications
Автор: Последнее обновление: 31.07.2019 - 14:30
Article

Using Intel® IPP Threaded Static Libraries

Q: How to get Intel® Integrated Performance Primitives (Intel® IPP) Static threaded libraries?

Автор: Последнее обновление: 31.07.2019 - 14:30
Блоги

Threading and the Intel® IPP Library – part 3 of 3

OpenMP Threading and Intel IPP

Автор: Paul F. (Intel) Последнее обновление: 31.07.2019 - 15:50
Блоги

Threading and the Intel® IPP Library – part 2 of 3

Threading Choices for Your Intel IPP Application

Автор: Paul F. (Intel) Последнее обновление: 31.07.2019 - 15:50
Блоги

Threading and the Intel® IPP Library - part 1 of 3

Introduction to Threading in IPP

Автор: Последнее обновление: 31.07.2019 - 15:50
Article

OpenMP* and the Intel® IPP Library

How to configure OpenMP in the Intel IPP library to maximize multi-threaded performance of the Intel IPP primitives.
Автор: Последнее обновление: 31.07.2019 - 14:30
Article

Programming for Multicore and Many-core Products including Intel® Xeon® processors and Intel® Xeon Phi™ X100 Product Family coprocessors

The programming models in use today, used for multicore processors every day, are available for many-core coprocessors as well. Therefore, explaining how to program both Intel Xeon processors and Intel Xeon Phi coprocessor is best done by explaining the options for parallel programming. This paper provides the foundation for understanding how multicore processors and many-core coprocessors are...
Автор: James R. (Blackbelt) Последнее обновление: 14.06.2019 - 12:10
Article

Element-wise Alignment Requirements for Data Accesses to be ABI-Compliant on the Intel® MIC Architecture

 

Compiler Methodology for Intel® MIC Architecture

Автор: Rakesh Krishnaiyer (Intel) Последнее обновление: 21.03.2019 - 12:08